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MSPM33C321A: HSADC full speed example seems to repeat data

Keith Barkley
Guru 44215 points

Part Number: MSPM33C321A
Other Parts Discussed in Thread: SYSCONFIG

I am trying out the HSADC full speed DMA example, but it seems to be repeating data. If I go by the number of samples I got, I am sampling at an absurdly high rate. If I remove all the repeats, I get a much more reasonable 4 MHz.

I have attached a sample file of the DMA area from a 100 kHz signal.

Is there a setting to fix this?

output3.txt 

  • 0
    TI__Intellectual 2460 points

    Hello Keith, 

    Thank you for this information. Let me kindly have a look at this and get back to you.

  • 0
    TI__Intellectual 2460 points

    Hello Keith, 

    First looking at the sysconfig settings, the transfer mode of DMA should be single and not block. Could you rectify that and let me know the results of that? 

  • 0 in reply to JOJO ARTHUR
    Guru 44215 points

    Single mode did not help

  • +1 in reply to Keith Barkley
    TI__Intellectual 2460 points

    Hello Keith, 

    This is quite strange. However, before you attach your ti_msp_dl_config.c, let's ensure here we are actually referencing the max frequency which is 9.4Msps with VDD>= 2.7V and External VREF >= 2.5V. The configured desired timer period, 106.25ns, is valid but the cycles used ins SEQ 1 configuration is wrong: it should be 6 cycles (to hit the minimum sample time of 37.5ns) instead of 16 cycles. Also, can you debug by setting a hardware breakpoint at the while loop and viewing the values of these registers below: 

  • 0 in reply to JOJO ARTHUR
    Guru 44215 points

    It looks like changing from 16 to 6 removed all the repeats.

    However, it looks like we are sampling at 5 MHz, my 100kHz signal is getting about 50 samples per cycle. I would expect 94 at 9.4 MHz sample rate

    Here are the registers you asked for

  • +1 in reply to Keith Barkley
    TI__Intellectual 2460 points

    Hello  Keith, 

    Glad to hear the 6 samples solved the repeating issue here. Nevertheless, regarding the exact 9.4Msps, I'm curious here because I assume there might be 1 or 2 cycle overhead because of the sampling capacitor resetting to half VREF and trigger path of Timer to the ADC. Keeping everything else constant, could you test by using a higher period time? Maybe 120ns? With this, I think every mechanism should settle between samples and we should be seeing 80 samples per cycle here. If 80 is seen, we can now reduce the timer period to the point where we don't see the expected results. 

    Also, a good indication of the sampling not happening on time will be to look at the overflow register, that is, ADCSOCOVF. A 1 in the 1 bit field indicates an event was triggered on SOC0 while an ongoing event was being serviced. Kindly let me know the results of this. 

  • 0 in reply to JOJO ARTHUR
    Guru 44215 points

    I switched to a timer period of 250ns, and that gave me 40 samples per cycle, just as expected.

    Actually, the 5 MHz is adequate for my needs, so I don't think I will pursue this any further.

  • 0 in reply to Keith Barkley
    TI__Intellectual 2460 points

    Got it and you're welcome Keith!

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