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MSPM0G3507: Memory Map

Dave Peter
Prodigy 60 points

Part Number: MSPM0G3507
Other Parts Discussed in Thread: SYSCONFIG

I'm trying to find the documentation for the memory map of the peripherals.

I can find some of the information in the Technical Reference Manual, but not enough to specifically know what memory location is associated with the function.

For example, the IOMUX registers on page 658 only give an offset of 4H, but in reference to what? Also, the PINCMx, the x refers to ? Is it the pin or some other reference.

 

   Thanks for your help

            Dave

  • 0
    Guru 103135 points

    The peripheral-register base addresses are listed in data sheet (SLASEX6C) Table 8-6.

    The PINCM indices are given in data sheet Table 6-2.

  • 0 in reply to Bruce McKenney
    Prodigy 60 points

    Thanks for the quick response Bruce.

    That's helpful, but I'm looking for more specifics (pardon if it is under my nose again)

    The PINCMx for example, if we were to want to update PINCM4, what would be the address? 

    It shows an offset of 0x4, but how large are the blocks? Seems like I remember a more detailed map when working on C2000 code.

          Again I appreciate the help,

                Dave

  • 0 in reply to Dave Peter
    TI__Mastermind 26218 points
    Dave Peter said:

    It shows an offset of 0x4, but how large are the blocks? Seems like I remember a more detailed map when working on C2000 code.

          Again I appreciate the help,

    In the code, this is an array.

    You can try to refer to the IOMUX related API:

        DL_GPIO_initPeripheralInputFunctionFeatures(GPIO_I2C_0_IOMUX_SDA,
        GPIO_I2C_0_IOMUX_SDA_FUNC, DL_GPIO_INVERSION_DISABLE,
        DL_GPIO_RESISTOR_NONE, DL_GPIO_HYSTERESIS_DISABLE,
        DL_GPIO_WAKEUP_DISABLE);
    DL_GPIO_initPeripheralInputFunctionFeatures(GPIO_I2C_0_IOMUX_SCL,
        GPIO_I2C_0_IOMUX_SCL_FUNC, DL_GPIO_INVERSION_DISABLE,
        DL_GPIO_RESISTOR_NONE, DL_GPIO_HYSTERESIS_DISABLE,
        DL_GPIO_WAKEUP_DISABLE);

    /**
 *  @brief      Configure a pin to operate with peripheral input functionality with optional features
 *
 *  @param[in]  pincmIndex The PINCM register index that maps to the target
 *                         pin to configure the peripheral functionality for
 *  @param[in]  function   Function to configure the pin for. See definition
 *                         of IOMUX_PINCMx_PF_xxx in the device header file.
 *  @param[in]  inversion         Enable Inversion of the pin input. One of @ref
 *                                DL_GPIO_INVERSION.
 *  @param[in]  internalResistor  Internal resistor to use. One of @ref
 *                                DL_GPIO_RESISTOR.
 *  @param[in]  hysteresis        Enable/disable Hystersis on the pin. One of
 *                                @ref DL_GPIO_HYSTERESIS.
 *  @param[in]  wakeup            Configure wakeup behavior for the pin. One of
 *                                @ref DL_GPIO_WAKEUP.
 */
__STATIC_INLINE void DL_GPIO_initPeripheralInputFunctionFeatures(
    uint32_t pincmIndex, uint32_t function, DL_GPIO_INVERSION inversion,
    DL_GPIO_RESISTOR internalResistor, DL_GPIO_HYSTERESIS hysteresis,
    DL_GPIO_WAKEUP wakeup)
{
    IOMUX->SECCFG.PINCM[pincmIndex] =
        function | IOMUX_PINCM_PC_CONNECTED | IOMUX_PINCM_INENA_ENABLE |
        (uint32_t) inversion | (uint32_t) internalResistor |
        (uint32_t) hysteresis | ((uint32_t) wakeup & IOMUX_PINCM_WCOMP_MASK);
    IOMUX->SECCFG.PINCM[pincmIndex] |=
        ((uint32_t) wakeup & IOMUX_PINCM_WUEN_MASK);
}

  • 0 in reply to Helic Chi
    Prodigy 60 points

    Thanks Helic,

    That's a little helpful, probably should look at some examples.

    I also seem to remember some type of Application Note that outlined the structure of the IO typically used by TI, but can't seem to locate it. Would you know where to find something like that?

            Dave

  • 0 in reply to Dave Peter
    Guru 103135 points

    The PINCM values as indices are in the IOMUX_PINCM enum (in m0p/mspm0g350x.h). To keep things lively, the PINCM array (in peripherals/hw_iomux.h) is off-by-one, [These are in the SDK. On my system they are in  C:\ti\mspm0_sdk_2_10_00_04\source\ti\devices\msp]

    The formula might resemble [for SPI0 SCLK]:

    #define SPIMSCLK_MUX  IOMUX_PINCM34    // PA12:IOMUX 34 as SPI0_SCK
#define SPIMSCLK_PF   3                // Per SLASEX6C Table 6-2

IOMUX->SECCFG.PINCM[SPIMSCLK_MUX] =
         (IOMUX_PINCM_PC_CONNECTED | IOMUX_PINCM_INENA_ENABLE | SPIMSCLK_PF);

    Sysconfig generates similar code.

    [Edit: Fixed code formatting]

  • 0 in reply to Bruce McKenney
    TI__Mastermind 26218 points
    Dave Peter said:
    I also seem to remember some type of Application Note that outlined the structure of the IO typically used by TI, but can't seem to locate it. Would you know where to find something like that?

    I don't know this~

    I think all your need can be found from source code, as   said above.

  • 0 in reply to Helic Chi
    Prodigy 60 points

    Sorry for the delay, appreciate the follow up.

    Not exactly what I was after, but have enough information to get things working.

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