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8MHZ crystal oscillator checking??

Other Parts Discussed in Thread: MSP430F149, MSP430F155

hi all.

  i got this code from ti example to add a external oscillator 8 mhz and its working properly  i got the 8 mhz frequency output  by means of reading the p5.4 pin.. and i did the slight modification i just included  the for loop to set and reset the port pin  p1.0 here the problem is if am checking the frequency at p1.0 means instead 8mhz  am getting only 0.8mhz .. what s the problem?? in the below code?

//******************************************************************************
//  MSP-FET430P140 Demo - Basic Clock, MCLK Sourced from HF XTAL
//
//  Description: Proper selection of an external HF XTAL for MCLK is shown by
//  first polling the OSC fault until XTAL is stable - only then is MCLK
//  sourced by LFXT1.  MCLK is on P5.4
//  ACLK= MCLK= LFXT1= HF XTAL
//  //* HF XTAL NOT INSTALLED ON FET *//
//  //* Min Vcc required varies with MCLK frequency - refer to datasheet *//    
//
//                MSP430F149
//             -----------------
//         /|\|              XIN|-
//          | |                 | HF XTAL (455k - 8Mhz)
//          --|RST          XOUT|-
//            |                 |
//            |             P5.4|-->MCLK = XTAL
//
//
//  M. Buccini
//  Texas Instruments Inc.
//  Feb 2005
//  Built with CCE Version: 3.2.0 and IAR Embedded Workbench Version: 3.21A
//******************************************************************************

#include  <msp430F155.h>

void main(void)
{
  volatile unsigned int i;
  WDTCTL = WDTPW + WDTHOLD;                 // Stop WDT
  P5DIR |= 0x10;                            // P5.4= output direction
  P5SEL |= 0x10;                            // P5.4= MCLK option select
  P1DIR |= 0x01;                          
 
  BCSCTL1 |= XTS;                           // ACLK= LFXT1 = HF XTAL

  do
  {
  IFG1 &= ~OFIFG;                           // Clear OSCFault flag
  for (i = 0xFF; i > 0; i--);               // Time for flag to set
  }
  while ((IFG1 & OFIFG));                   // OSCFault flag still set?

  BCSCTL2 |= SELM_3+SELS+DIVM_0;                        // MCLK= LFXT1 (safe)

  for (;;)
 
  {                                 
      P1OUT |= BIT0;  // SET P1.0
      P1OUT &= ~BIT0; // RESET P1.0
  }  
      
      
}

  • karthik raja said:
      for (;;)
       {                                 
          P1OUT |= BIT0;  // SET P1.0
          P1OUT &= ~BIT0; // RESET P1.0
      }  

    So this most likely compiles to

    loop:
    BIS #1, P1OUT
    BIC #1,P1OUT
    JMP loop

    BIS and BIC each require 4 clock cycles (read instruction, read P1OUT address, read from P1OUT, write back result to P1OUT)
    The JMP takes two cycles. Sums up to 10. And 8MHz/10 = 0.8MHz.
    On P1.4 to P1.7 it would even take two more cycles, since the constant generator can only generate the lower 4 bits.

    That's the difference between a hardware solution (hardware output of MCLK to a port pin) and software (generating an output signal by toggling port pins)

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