spi

I hope I understand your worry correctly...

Once an ISR has started executing, it will continue so until it returns. It makes no difference whether you manually clear the IFG bit, read teh UCBxIV register (which also resets teh IFG bit)  reset the IE bit or reset the whole hardware module (with SWRST).

However, if you set SWRST, no further interrupts will come for this specific ISR, since you disabled the hardware that generates them. Everything else wouldn't make sense.
Other interrupts (from timer, other USCI module etc.) will still come. Also, USCIxA and USCIxB are independent.

hello,

thank you for replying to my problem. i have one more question - suppose if i set my SWRST within the isr, perform some operation while still in the isr and again reset the SWRST, then will the system still work?? as in will it still be able to receive interrupts for that particular isr??

regards,

abhishek

It doesn't matter when and where oyu program teh USCI. CPU (code execution) and hardware modules (USCI) are independent of each other.
The only important thing is that the USCI 'rings a bell' (sets the IFG bit) and the CPU reacts on it with executing the ISR (if the GIE and the individual IE bits are set).

Teh influence of interrupts on the CPU is:

if ( GIE && ( (IE0 && IFG0) || (IE1 && IFG1) || ...)) then execute an ISR

This is checked after every CPU instruction (in hardware, of ourse). It is unimportant how the IE and IFG bits have been set and when. You can even manually trigger an interrupt by setting an IFG bit, and if in your ISR you don't clear the IFG bit that triggered the interrupt, it will be executed over and over again.

Since during an ISR, GIE is clear, no other ISRs are executed. So all that counts is the status of IE and IFG bits when you exit the ISR. How this status is achieved is unimportant.

However, as long as SWRST is set, the USCI does not send or receive anything, and setting SWRST even aborts currently active operations. SWRST (SoftWare ReSeT) resets the USCI state machine and keeps it on start position until SWRST is cleared. So the change of vital parameters won't mess-up the state machine.

Hello Sir,

thank you for explaining these concepts to me. i am basically trying to create an application wherein i am controlling various operations of CC1101 low power rf module by TI. so in that in one particular operation i write a data byte to the transceiver chip over SPI and after writing that byte i have to check for the logic level of the MISO pin on cc1101. so what i do is that when i am in the ISR, and after transmitting that byte, i set the SWRST bit and choose I/O functionality for port3 pin (USCIB0 where i m using SPI) and then check if the SLAVE OUT pin is high or low after checking i reset the SWRST bit to re-enable spi mode. all this is done in the same ISR without affecting the IE or IFG bits. now here are my questions:

Q1 can you tell me if my current approach is correct or not?

Q2 can i check the logic level of the pin while in SPI mode itself?

Q3 once i set SWRST bit then are the register settings for SPI retained or are they lost and i have to set those values again the next time i use SPI?

regards,

abhishek agarwal

abhishek agarwal said:

after transmitting that byte, i set the SWRST bit and choose I/O functionality for port3 pin (USCIB0 where i m using SPI) and then check if the SLAVE OUT pin is high or low

You don'T need to disable the USCI module just to switch the por tpin from module to I/O. The PxSEL register controls the por tlogic independently of the module action (there are some exceptions on port pins with analog functionality, where the module sometimes overrides PxSEL)

But not even this is necessary. If you check the port schematics in the datasheet, you'll probably see (this is device-dependent, there are few devices where it won't work) that PxIN still works even if PxSEL is set. Especially if the pin is input (like MISO in master mode).