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CC430F5135 XT2 oscilator fault when it is not used!!!

Marcin Gajewski
Prodigy 95 points
Other Parts Discussed in Thread: CC430F5137

Hello,

I have a problem whith UCS module. Program debuggin stops on testing oscillator fault flag

 // Loop until XT1,XT2 & DCO fault flag is cleared
  do
  {
    UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
                                            // Clear XT2,XT1,DCO fault flags
    SFRIFG1 &= ~OFIFG;                      // Clear fault flags
  }while (SFRIFG1&OFIFG);                   // Test oscillator fault flag
 

In my program I using only DCOCLK and REFOCLK (trimmed 32,768 kHz) without XT1 and XT2. Program stops on marked line.

I even switch off by software XT1 and XT2 and the fault flag still apears. The line:

SFRIFG1 &= ~OFIFG;

suppose to clean the flag, but it can't. In datasheet of cc430 family is cleary written that XT2OFFG can be clean via software.

When I comment this point of the program, everything working fine, so did before. I hope that someone had similar problem and solved it.

Regards


  • 0
    Guru 92251 points

    Looking at a CC430F5137 in the debugger shows that after reset:

    - XT1LFOFFG is set

    - XT2OFFG is clear

     XT1LFOFFG is set at reset because due to default registers settings after reset:

    a) XT1 is used to source the FLL reference select (controlled by the SELREF bits in UCSCTL3)

    b) XT1 is used to source ACLK (controlled by the SELA bits in UCSCTL6)

    Is there anything in your code which could cause XT2 to be selected as clock source, which would lead to XT2OFFG being set and not being able to be cleared?

  • 0 in reply to Chester Gillon
    Prodigy 95 points

    My main code of UCS is:

     UCSCTL5 |= XT2OFF+XT1OFF;
      UCSCTL3 |= SELREF_2;                      // Set DCO FLL reference = REFO
                                                  //wbudowany dokladny zegar 32,768kHz
      UCSCTL4 |= SELA_2+SELS_3+SELM_3;          //ACLK = REFO, MCLK=SMCLK=DCOCLK.
      UCSCTL5 |= DIVS_4;                        //SMCLK/10=MCLK


    If you like me precisly at line
     UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);

    you can see that this flag should be claer by software, but when debbuger is procced this line nothing changes.

    My program can't cause beceause function of UCS is called first and set up like shown upper.

    Before it worked, everything was fine.

  • 0 in reply to Marcin Gajewski
    Guru 92251 points

    The error is in the following line:

      UCSCTL4 |= SELA_2+SELS_3+SELM_3; //ACLK = REFO, MCLK=SMCLK=DCOCLK.

    Because this ORs bits into the power-up value of UCSCTL4 it ends up setting:

    a) SELA = 010 = REF0CLK

    b) SELS = 111 = Reserved for future use. Defaults to XT2CLK.

    c) SELM = 111 = Reserved for future use. Defaults to XT2CLK.

    This causes XT2CLK to be selected, and the XT2OFFG fault flag to be set.

    The line should be: 

      UCSCTL4 = SELA_2+SELS_3+SELM_3; //ACLK = REFO, MCLK=SMCLK=DCOCLK.

     

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