ADC MSP430G2553

Hello Aamir,

I had a look in the Internet and found following explainations for some of your questions in your first paragraph.

Break-before-make switches are those that will only complete one circuit at a time, leaving an interval of time between the time one circuit opens and the next circuit closes. This can also be referred to as a non-shorting type switch.

Make-before-break switches are those that will complete a new circuit before breaking an old one. With this type of function, the next contact is made or closed before the previous contact is broken or opened. This can also be referred to as a shorting type switch.

A T-switch consists of two analog switches in series, with a third switch connected between ground and their joining node. This arrangement provides higher off-isolation than a single switch. The capacitive crosstalk for a T-switch turned off typically rises with frequency due to the parasitic capacitances in parallel with each of the series switches.

Regards

Marco

Hi Maro,

Thanks 4 ur rply.Any information on othr points also.

Aamir Ali said:

are isolated from the A/D and the intermediate node is connected to

This is an extension to the T-switch. Looking at Marcos picture, each analog input has such a T switch, all outputs are connected to the ADC. The easy way would have been to have just n switches for n inputs. With a certain capacitive coupling from one inptu to the next across open switches. The use of a T switch ensures that between any two inputs, there is at least one point between them that is connected to GND and prevents any crosstalk. This middle area in teh T switch that is connected to GND if the input is nor used, is the intermediate node.

Aamir Ali said:

charge redistribution method

You'll find a very detailed explanation here.
It seems that a precision ladder of capacitors is easier to produce than a ladder of resistors. Originally, an SAR worked by producing an output voltage of 1/2 Vref and comparing the inut against it, producing the MSB of the result. Then the MSB of the DAC was set to the MSB of the output and the next bit was set to 1 and again compared to the input etc.
There was a storage capacitor needed and the size of the capacitor was unimportant.
The charge redistribution uses the process of redistributing the sampled charge between different capacitors, which also works as sort of a DAC. If the values of the capacitors can be easier matched on the die than the values of resistors (and it is possible, since linear resistors on a silicon die aren't trivial), the charge redistribution method provides higher precision if the capacitors are on-die (with external ones you wouldn't be able to properly match them). It is also possible, that this method requires less current. A resistor ladder requires a constant current to produce a voltage. Capacitors only require a charge and (except for internal leakage and the comparator input current) provide a static voltage level withut any current consumption.

Aamir Ali said:

The reference generator includes a band-gap voltage source and a separate buffer

A band-gap reference uses the potential difference of two states of an atom (silicon, I'd guess :)
The simplest form is a diode. If you put a current through a diode, you'll get a voltage. If the current changes, the voltage changes. However, a current change of, say 10% will only cause a voltage change of, say, 1% (around the proper working point). So if you can regulate the current fairly well (e.g. by resistors), the precision of the produced voltage will be a magnitude better. By using two diodes (or rather, two transistors), one with and one without a base resistor, but same base voltage, you can regulate the current and therefore the base voltage very well. Also, influences of temperature can be suppresed.

Teh separate buffer, well, I don't knwo what it is. An internal capacitor, or a driving loop, that follows the band gap reference output. I don't know. However, the buffer can be used or not and influences ADC performance (maximum sampling frequency) and current consumption.

Aamir Ali said:

Integral linearity error,Differential linearity error ,etc. What is their meaning.

Differential Linearity error (also called Differential No-Linearity, DNL) is the difference between what a single step in the ADC output means (Vref/(2^n-1)) and what the acutal input voltage range is that causes a certain ADC result.
let's say the ADC resolution is 1mV. So 0 to 0.5mV will give a result of 0, 0.5 to 1.5mV will give 1 etc. This would be a DNL of zero. If, however, you get a result of 1 for 0.5 to 1.6mV, then you have a 0.1mV DNL, as the voltage range that caused a reading of 1 was 0.1V larger than it should be. A DNL > 1LSB causes a missing code, a value that will never appear on the output.
In short, DNL indicates the deviation from the ideal analog step size that corresponds to an 1LSB change in the output code.

The integral linearity error ILE, also called Integral Non-Linearity is the maximum of the integrated DNL.
So if the DNL is -0.1 for x=1, the ILE is 0.1 at this point. If for x=2, the DNL is again -0.1, the ILE is 0.2. If now a DNL of +0.2 follows, the ILE is 0 again (however, it's maximum so far was 0.2)
The ILE is calculated after correcting gain and offset errors (end point method). So at x=0 and x=max, the ILE is always zero. Using the 'best fit' method, an additional offset is introduced so minimize the ILE, effectively centering it. In this case x=0 and x=max have the same value (with opposite sign). This is better for precision calculations in applications where the absolute voltage is unimportant, but the relative voltage is important.
The maximum ILE is, how much the actual curve of input voltages, that cause a linear increase of the output value, strays from the ideal straight line.

Aamir Ali said:

4. What is error in ADC10. is it +-1LSB.

No. The maximum error is a combination of many diferent things.
The quantization error of any ADC (no matter what bit size) is -1LSB, or +- 1/2 LSB (depending on offset adjustment). To this you'll have to add the maximum ILE. And offset/gain error, if not compensated.

The maximum error if your reference is exact and you just take the formula U=x*Vref/((2^n)-1) is +-5LSB. If you compensate for offset and gain, the maximum is +-1.5LSB (+-1LSB for DNL and +-0.5LSB for quantization)

Well, the error introduced by an inaccurate reference is usually larger, at least in the upper region. :)