• State
  • Locked Locked
  • Replies 6 replies
  • Subscribers 79 subscribers
  • Views 1655 views
  • Users 0 members are here
Support feedback
Options
Options
Similar topics

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Regarding MSP430 MCU compatibility

souvik metia
Intellectual 545 points
Other Parts Discussed in Thread: MSP430FG4618

Hello friends, I have a quarries regarding MSP430 processor series which is like that....

                      I want to interface a ASIC with my msp430fg4618 mcu, but in ASIC user guide they ask for the following processor series which are compatible with

                                                                                                               INTEL : 80C31, 80X86

                                                                                                         SIEMENS : 80C166/165/167

                                                                                                     MOTOROLA : HC11-, HC16-, and HC916 types

I searched for those given processor series and i found that they are follow Havard architecture some are CISC, RISC architecture. They are 8bit and 16 bit as well. But i can't understand that is my mcu compatible or not with the above specification,because it is based on RISC architecture and 16 bit as well.

I also see that my TI mcu has no Address bus pin and Data bus pin which will communicate with the ASIC pin. So can i use my GPIO as a Address bus and Data bus( of course if my MCU pass the compatibility) ?

Here is the ASIC pin Diagram and pin description.

 

please reply.....

  • 0
    Guru 227245 points

    All those mentioned processors do have an external address/data bus. So you can embed teh ASICs registers/memory into the processors memory space. Or (in case of the X86) access it using a specific peripheral bus with the "out address,value" instruction.

    The MSP does not have an external address/data bus. You'll have to emulate it by GPIO programming. e.g. put address on PortA (conenctes to AB0..10), put data on Port3 (connected to DB0..7), pull 'write' line on Port4 (connected to R_W or ALE or whatever the protocol requires) etc.
    This is, of course, slow and clumsy. But the only way.
    Teh advantage is: you can pick any one of the supported ways to interface the ASIC fo rsoftware implementation :)

  • 0 in reply to Jens-Michael Gross
    Intellectual 545 points

    thanks for reply Jens, I am not able to understand properly, can you little elaborate the example so that i can understand it properly. Again thank you for your reply.

  • 0 in reply to Jens-Michael Gross
    Intellectual 545 points

    you mean to say like that what i have just colored the pins( Connection between the two processor). But how can i set the GPIO like Address bus, Data bus RD, WR, ALE etc.

    Can i program the GPIO so that it can do the Address, Data bus, ALE function?

    Please reply ....

  • 0 in reply to souvik metia
    Guru 227245 points

    In your diagram, ou forgot AB8, AB9 and AB10. There are 11 address bits. You should connect them to P2.0..P2.2,a s you can access P1 and P2 together as PA with 16-bit instructions as if they were a 16-bit port.
    Maybe you'll also need to set the MODE pin to a specific level, I don't know the bus specifics.

    How to do it. Well, one rough example:

    Write 0x7FFFF to PADIR, to make P1 and P2 outputs.
    Write 0x03 to P4OUT, then 0x03 to P3DIR, to make the two signals a high output.

    To write the value 0x12 to the address 0x1234 of the chip, write 0xff to P3DIR (to make P3 output), tehn 0x12 to P3OUT. The value now appears on P3 and therefore on DB0..7

    Next write 0x1234 to PAOUT. Now 11 bit address and 8 bit data are availabel on the MSP ports.

    Next step is clearing the P4.1 bit (or whatever is connected to R_W). It is done by
    P4OUT &= ~BIT0;

    Last step is clocking the data in. Most likely (See the bus details of the chip) it is done by pulling and releasing ALE:

    P4OUT &= ~BIT1; P4OUT |= BIT1;

    When ALE goes low (ALE most likely means Address latch Enable), teh chip will write what appears on its DBx pins to the address on its ABx pins.

    Reading is similar. This time, write 0xff to P3DIR to make it input.
    then release the R/W signal:
    P4OUT |= BIT0;

    When you now pull and release ALE, with releasing ALE, the content of the address on ABx will appear on DBx and you can read it by reading the P3IN register.

  • 0
    Guru 92251 points

    It looks like the ASIC is powered from +5V, therefore level shifters will be required between the ASIC and the msp430fg4618 (supply voltage range 1.8V to 3.6V)

  • 0 in reply to Chester Gillon
    Guru 227245 points

    Chester Gillon said:
    level shifters will be required

    uh-oh! This adds another level of complexity to the bidirectional data transfer on DB0..7.

    For the other lines, a level shifter is maybe not necessary, if the MSPs VCC voltage level is accepted as high by the ASIC. It woudl be a good idea to pwer the MSp with 3.3 or even better 3.6V.
    And if power consumption is not an issue, maybe a simple series resistor of 1-2kOhms might be sufficient on the DBx lines. If the ASIC outputs 5V, a 1k resistor will limit the current through the clamp diodes to (5V-(VCC+0.2V))/1k = 1.5mA on VCC=3.3V, which is acceptable (maximum rated curent through the clamp diodes is 2mA).
    Especially since this happens only during ALE low, so for a short time.

**Attention** This is a public forum