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Hi,
let me try to learn how SPI works in the Launchpad + MSP430G2452. My code (I wanted to do this based on interrupts but I was not having any success so I have to try simpler for now) is the following:
#include <msp430g2452.h>
#include <intrinsics.h>
#include <stdint.h>
uint8_t RXdata;
void main (void) {
uint8_t i;
WDTCTL = WDTPW + WDTHOLD; // Stop watchdog timer
// pin most energy saving configuration
P1DIR = 0xFF; // All P1.x outputs, it saves energy MSP430x2xx Family User's Guide
P1OUT = 0; // All P1.x reset
P2DIR = 0xFF; // All P2.x outputs
P2OUT = 0; // All P2.x reset
// Pull resistors on unused pins// Enable SDI, SDO, SCLK, msb first, master, enable output, latch data
USICTL0 = USIPE7 | USIPE6 | USIPE5 | USIMST | USIOE;
// Write then read (CPHA = 1 -> CKPH = 0), SPI not I2C, enable interrupt
USICTL1 = USIIE;
// SCLK = SMCLK / 128, clock idles high (CPOL = CKPL = 1)
USICKCTL = USIDIV_7 | USISSEL_2;
// Release USI from reset
USICTL0 &= ~USISWRST;
// SPI transfer
USISRL = 0x46; // this is a READ, a WRITE would be 06
P1OUT |= 0x40; // CS from low to high
USICNT = 8;
for (i = 0xFFFF; i > 0; i--); // Delay
while (!(USIIFG & USICTL1)); // Counter clear?
// this second byte is only important when writing
USISRL = 0x69;
USICNT = 8;
for (i = 0xFFFF; i > 0; i--); // Delay
while (!(USIIFG & USICTL1)); // Counter clear?
P1OUT &= ~0x40; //CS from high to low
RXdata = USISRL;
// Enter LPM0 & configure to be able to leave it by interrupt
_BIS_SR(LPM0_bits + GIE);
}
After trying to write some value to the slave's SPI register (same code as above but with opcode 06), when I try to read the destination register, I only obtain 00 in USISRL and I should obtain... 0x69. :( Argh! I think I've configured all correctly! Below you can see a WRITE transaction as expected by the slave device, and a READ transaction.
My questions are:
Please let me know your opinion! :) It is my first week with MSP430 so please be benevolent :)
The code doesn't set P1SEL.x or P1SEL2.x bits required to select the port 1 pins for the USI module.
The P1SEL and P1SEL2 registers are cleared at reset which configure the port1 pins as just GPIO.
See Table 17. Port P1 (P1.5 to P1.7) Pin Functions in the MSP430G2x52 datasheet SLAS722E for the P1SEL.x or P1SEL2.x settings required.
:(
Yeah, I have not seen this in any of the examples of the TI resource explorer in CCS5. Is this possible?
I think I'm missing something like:
P1SEL |= 0xE0; // set P1.7, P1.6, P1.5 for SPI functions
Tomorrow I'm gonna give it a try.
Thanks a lot.
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