HOW TO USE SPI CLOCK TO 2 MEGAHERTZ USING THE UCS?
COMO USAR EL SPI CLOCK A 2 MEGAHERTZ, USANDO EL UCS?
#include "msp430x54xA.h"
#include "hal_pmm.C"
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
SetVCore(PMMCOREV_1); // Set VCore = 1.6V for 12MHz clock
P1DIR |= BIT0; // P1.0 output
P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins
P11SEL |= 0x07; // P11.0,1,2 for debugging purposes.
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 125; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (125 + 1) * 32768 = 4.0MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 4.0 MHz / 32,768 Hz = 125000 = MCLK cycles for DCO to settle
__delay_cycles(125000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test XT1 fault flag
P3SEL |= 0x31; // P3.5,4,0 option select
UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB; // 3-pin, 8-bit SPI master
// Clock polarity high, MSB
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0BR0 = 0x02; // /2
UCA0BR1 = 0; //
UCA0MCTL = 0; // No modulation
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt
while(1)
{
P1OUT ^= BIT0; // Toggle P1.0
__delay_cycles(2000000); // Delay
}
}
