This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Need help with 4 pin JTAG

Hi

We are developing a new product using the MSP430F5500. Basically, the MSP is set up as a "slave" to a "master" CPU and we're looking to be able to field update the MSP from the other CPU using the 4 wire JTAG interface. As a reference, I've been using the Replicator for the MSP430Xv2 software along with the JTAG_App_Note_slau320c document as a reference. I'm currently stuck and am hoping someone could provide some advice. Here's what I'm doing: 1. Reset the MSP and activate the JTAG lines (TDI, TDO, TMS, TCK, TEST). 2. Using RST and TEST go through the 4-wire JTAG entry sequence. 3. Reset the TAP. 4. IR shift the bypass instruction (IR_BYPASS) while reading the TDO lines. I see the JTAG ID (0x91) as expected. 5. Do a fuse check by IR_Shift(IR_CNTRL_SIG_CAPTURE) then DR_Shift16(0xAAAA) 3 times. Each time I read zero back from TDO. 6. Try to put the MSP into JTAG mode by IR_SHIFT(IR_CNTRL_SIG_16BIT) -- DR_Shift16(0x1501). 7. Read back the control signal register ... IR_Shift(IR_CNTRL_SIG_CAPTURE) -- DR_Shift16(0). Also check for the JTAG ID again at this point and it's still clocking in on TDO. 8. Repeatedly check for the TCE0 bit of the control signal register to be set for CPU synchronization (DR_Shift(0)). And here is where I get stuck. I never see TCE0 being set. In fact every data register shift I do returns zero back on TDO even though every instruction register shift I do always returns the correct JTAG ID. I've tried a few different instructions (IR_COREIP_ID, IR_DEVICE_ID) and I always get a flat TDO line when I try to do the data register shift afterwards. I've been checking the clocking using a logic analyzer and played around with the timing and all. But the fact that the JTAG ID gets shifted out TDO on every instruction I shift in tells me the timing is probably OK. I'm thinking maybe the FSM isn't getting setup properly for a data register shift but I have yet to see it in the logic analyzer traces. Again I'm using the TI Replicator for the MSP430Xv2 code for reference. I should also mention that while we are going to use the F5500, our current boards have the F5508. Any advice would be appreciated. Thanks Mark
  • Mark White said:

    I never see TCE0 being set. In fact every data register shift I do returns zero back on TDO even though every instruction register shift I do always returns the correct JTAG ID.  

    I am having a similar issue... anyone have experience with programming for JTAG?

  • hi there,

    I have not done what you are doing but I think the issue is that the MSP430F55xx is a CPUX part with 20 bit addressing versus 16,  Check out the newest SLAU320d   (d version) of the JTAG programming note.  I think you need to use the 20 bit address shift in step 6.  (ref section 1.2.4.1.1 of the newer SLAU320d).

    Hope this helps,

    Steve S

**Attention** This is a public forum