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queries for ADC12 &OPAMP

ASHISH PATEL
Prodigy 230 points
Other Parts Discussed in Thread: MSP430FG4618

i have some confusion in ADC12 is that what is the SHT0_4    ??

then what should be minimum clock at that time what should be the MCLK ??

how its related to the MCLK and ADC12clk ??? 

if i want to trigger my ADC to timer A what should be care taken  for it ???

@ doubts for the OPAMP ??

i m using MSP430FG4618 so OPAmps are there what is the trans conductance of the that opamp if feedback resister is 5M and feedback capacitor 3.3pF ??

if possible then plz give me on which method u calculate it actually i m working with pulse oximeter so i need trans impendance amplifier but i don't how should i calculate it  

what is the gain bandwidth product of that opamp ???

 in my program its there i want to under stand actual relation between those things ...please help me

  ADC12CTL0 |= ADC12ON + MSC + SHT0_4 + REFON + REF2_5V;
    ADC12CTL1 |= SHP + SHS_1 + CONSEQ_1;     // Use sampling timer, single sequence,
    ADC12CTL1 |=  ADC12SSEL_1 + ADC12DIV_2  ;                                        // TA1 trigger(SHS_1), start with ADC12MEM0
    ADC12MCTL0 = INCH_0 + SREF_1;           // ref+=Vref, channel = A1 = OA0
    ADC12MCTL1 = INCH_1 + SREF_1 + EOS;
    ADC12MCTL2 = INCH_4 + SREF_1 + EOS;       // ref+=Vref, channel = A1 = OA0
    ADC12IE |= BIT1 + BIT0 + BIT4;                         // ADC12MEM1 interrupt enable
    ADC12CTL0 |= ENC; 

  • Guru 227245 points

    ASHISH PATEL said:
    what is the SHT0_4 

    SHT0_4 selects the 4th (0-based) combination of SHT0x bits. These bits control the duration of the sampling time in the sample-and-hold stage. The value thar corresponds to the selection is foudn in the users guide and means ADC12CLK ticks. Minimum is 4 ticks (SHT0_0).

    The sampling time should be chosen short enough for your required sampling frequency, but long enough, to allow the sampling capacitor to be charged depending on your signal impedance (the higher the input impedance, teh higher the minimum sampling time)

    ASHISH PATEL said:
    then what should be minimum clock at that time what should be the MCLK

    Conversion requires 13 clock cycles (for 12 bit conversion). The clock used for the ADC must be fast enough so the sampling capacitor won't deplete significantly during the time the conversion takes. IIRC, ~200kHz is the minimum. THe maximum is ~6MHz, depending on device. The default settign is to use the internal MODOSC, which has 5MHz.
    There is no relation to MCLK. But SMCLK or ACLK can be optionally used instead of MODOSC.

    ASHISH PATEL said:
    if i want to trigger my ADC to timer A what should be care taken  for it ?

    There are two ways to trigger ADC12 with a timer. Also, there are different timer sources.
    The ADC12 is triggered by the (internal) state of the CCRx output signal (see Timer PWM operation). Three CCR units from TimerA or TimerB are available as triggers.
    The SHP bit controls, whether the PWM output of the timer just triggers a conversion, or whethe rit directly controls the duration of the sampling stage. In the latter case, SHP must be clear and oen edge of hte PWM signal opens the sampling gate, and at the second edge, the sampling gate is closed and conversion starts (and is finished 13 ADC12CLK pulses later).

    ASHISH PATEL said:
    @ doubts for the OPAMP

    Sorry, I can't tell you anything that isn't in the datasheet already. I never used it myself, and so I never did any own calculations or inquiries.

    ASHISH PATEL said:
        ADC12MCTL1 = INCH_1 + SREF_1 + EOS;
        ADC12MCTL2 = INCH_4 + SREF_1 + EOS;       // ref+=Vref, channel = A1 = OA0

    The sequence ends with the first channel that has EOS bit set. So a sequence starting on ADC12MEM0 woudl end with ADC12MEM1, and a sequence started on ADC12MEM2 would and there too immediately. Probably not what you want. Possibly a copy/paste error :)

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