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RAM retention mode

Leonardo Steinfeld
Prodigy 120 points

Other Parts Discussed in Thread: MSP430F5438

Hi,

I have a question regarding the RAM retention mode of the MSP430F5438.

The family manual (SLAU208B–June 2008–Revised January 2009) specify (page 296): "Low-power modes: In all low-power modes, the CPU is switched off. As soon as the CPU is switched off, the RAM enters retention mode to reduce the leakage current."

Moreover, the datasheet of the MSP430F5438 (page 17) says "Each sector 0 to n automatically enters low power retention mode when possible."

I want to know exacty how each sector is managed to switch to low power retention mode. I want to predict/calculate energy saving according to how the data is accessed from the RAM. If also someone can tell me the power spent by block in each power mode it would be great!

Thanks in advance for any help.

Best,

Leo

  • 0
    TI__Guru 70392 points

    Leo,

    the retention mode is handled transparently to the user. Whenever the CPU is off all of the RAM sectors enter retention mode. So there isn't much you can optimize by trying to allocate your data in a certain way.

    However if you are trying to squeeze the last couple of 100nA's of current, you should look at allocating your data (and your stack!) such that you can completely disable certain sectors RAM. Especially at higher temperatures, when leakage current becomes more dominant, you should see some amount of improvement over the datasheet numbers.

    I don't have any specific numbers handy, but you could do some bench testing with different operating scenarios to see what you can get. Needless to say that for this you would need a very clean PCB, all I/Os terminated properly, and of course adequate measurement equipment.

    Regards,
    Andreas

    BTW, the current MSP430F5xx Family User's Guide is at revision "E" (not "B")
    http://www.ti.com/lit/pdf/slau208

  • 0 in reply to Andreas Dannenberg
    Prodigy 120 points

    Andreas,

    Thanks for your quick answer.

    It is clear that when the CPU is off all the RAM sectors enter into retention mode, and that the programmer can disable certain RAM sectors (setting the respective RCRSyOFF). But, according to the specific chip datasheet (I did not look for in other chips datasheet) seems it is possible to enter in low power retention mode any sector intependently. I was wondering how that is managed.

    Regards,

    Leo

  • 0 in reply to Leonardo Steinfeld
    TI__Guru 70392 points

    Leo,

    All blocks on the device automatically enter retention mode upon entry to any LPM mode. The user cannot control this aspect on a block by block basis. He can control on a block by block basis if a block of RAM is completely disabled. But we'll see if we can add some typical numbers to a future datasheet revision to clarify this behavior a little better.

    Thanks and Regards,
    Andreas

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