This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

How can DMIPS greater than MIPS for a MCU

Other Parts Discussed in Thread: MSP430G2553, MSP430F5438

1. If we look at MIPS (million inst per sec), it is calculated using what minimum time MCU will take to execue any instruction. Like for msp430g2553, min time is 62.5 ns or have 16MIPS. MCU can't run faster than that right.

2. But DMIPS are like e.g  1.25DMPIS/MHZ. How can MCU go faster than MIPS. Even if dhryatone has some code . How can it go faster than that, MCU can't solve inst faster than mips in any case

  • Can we calculate DMIPS for MSp430 also.

    What purpose does it solve to programmer.

  • Hi Aamir,

    Dhrystone MIPS (DMIPS) allow you to compare processors that have different instruction sets. While two processors may have the same MIPS (how many instructions they can execute in a second - basically clock speed), it can take the two processors a different number of instructions to complete the same calculation or task because they have different instruction sets. So DMIPS measures not just instructions per second but gives an idea of how long overall it will take one processor to perform a task versus another, taking into account the different number and kinds of instructions the processors will have to use to complete the task. Because of this, DMIPS can't just be calculated from MIPS, you have to actually measure them using the Dhrystone benchmark testing. And this is also why DMIPS can be greater than 1 DMIPS/MHZ - because due to instruction set, 1 instruction can actually be getting more done than 1 instruction on another processor. For example a 16 bit architecture is likely to be more efficient than an 8-bit one for some tasks.

    You might be interested in this app note - it's not the most current but includes some benchmarking on an MSP430F5438 (including some Dhrystone tests):  www.ti.com/lit/pdf/slaa205

    Regards,

    Katie

  • Hi Katie, Thanks for sharing valueable information.

    Does that mean Dhrystone code (as given in above AN) is first computed by some standard machine. After that same code is then executed on desired machine. Like MSP430

    Final results is comparison of two which gives DMIPS.

    Did I get it right? If yes, what does the processor used initially for comparison.

  • Katie Enderle said:
    For example a 16 bit architecture is likely to be more efficient than an 8-bit one for some tasks

    Or, whcih does a huge difference, the MSPs indirect autoincrement addressing mode combines offset/index calculation, operation and increment of the index into one instruction where other processors require two or even three. The BIC instruction for clearing a bit will on other processors require an inversion of the argument and then an AND operation (as you do it in C). (BIS, however, is identical to OR).

    Also, the constant generator saves one clock cycle for certain constants like 0, -1 and 1,2,4,8, which happen to be the status bits if used on the status register. Allowing 1-cycle-instructions where other processors would require two due to the additional parameter.

    However, the Dhrystone benchmark, as all benchmarks, only measures things that were in the scope of the developers. And some smart inventions of later processor types won't be taken into account, while todays smart compilers would of course use them to produce smaller or faster (and often both) code.

  • Note that a DMIPS measurement also includes the quality of the compiler.

    IIRC, 1 DMIPS was assigned to the performance of a VAX780.  http://en.wikipedia.org/wiki/DMIPS claims one DMIPS means about 1700 dhrystone loops per second.

    DMIPS per MIP is (in some sense) an evaluation of the efficiency of the computer architecture (for the specific purpose of running the dhrystone benchmark.)

  • westfw said:
    Note that a DMIPS measurement also includes the quality of the compiler.

    Sure. However, if the benchmark does not make use of functionality that makes one processor mroe efficient than the other, then you won't see it in the benchmark result.

    Examples: a benchmark that does not uses the stack won't show that a processor with a hardware stack may be much faster than one with the typical 'software' stack.
    If the benchmark only uses 16 bit integer arithmetics it won't show the huge speed gain of a 32 bit processor. The performance gain from autoincrement indexed addressing modes won't show up if no tables are accessed/iterated.

    Having 12 general-purpose registers won't help if the benchmark is happy with two.

    westfw said:
    (for the specific purpose of running the dhrystone benchmark.)

    Yes, that's what I meant. And usually, people always pick the benchmark where their product excels while the others look bad.

**Attention** This is a public forum