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Watchdog Timer Control Rregister

william hutt
Prodigy 110 points
Other Parts Discussed in Thread: MSP430F148

MSP430F148

How are the timer intervals derived when using the SMCLK and ACLK?

I am using a 32768Hz xtal.
I am also using the Watchdog mode.


Watchdog timer interval select:  From page 10-8 of SLAU049D

00 Watchdog clock source /32768
01 Watchdog clock source /8192
10 Watchdog clock source /512
11 Watchdog clock source /64

In addition I found the following table:

SSEL  IS1 IS0 Interval [ms]

    0       1     1    0.064  tSMCLK × 2e6
    0       1     0        0.5  tSMCLK × 2e9
    0       0     1           8  tSMCLK × 2e13
    0       0     0         32  tSMCLK × 2e15 <– Value after PUC (reset)

    1       1     1        1.9  tACLK × 2e6
    1       1     0      16.0  tACLK × 2e9
    1       0     1       250  tACLK × 2e13
    1       0     0     1000  tACLK × 2e15

 

 

  • 0
    TI__Expert 7845 points

    Timer interval depends on the value of SMCLK or ACLK. For example, if you choose a 32768 Hz ACLK as the Watchdog clock source, the timer interval (in interval timer mode) will be 1 sec, if Interval timer select is 00 (32768/32768).

    My recommendation is to look at the code examples "fet140_wdt_01.c" & "fet140_wdt_02.c" in the following zip file:
    http://www.ti.com/lit/zip/slac015

    These code examples can be found at:
    http://www.ti.com/msp430codeexamples

    Upon startup the watchdog comes up in watchdog mode (not interval timer mode), which resets the device every 32*SMCLK. The code examples show you how to configure the watchdog as an interval timer.

  • 0 in reply to Harman
    Prodigy 110 points

    My 32768 Hz Xtal is across the Xin and Xout pins of the MSP430.

    I am using the watchdog mode not the interval mode.

    When the system starts up an interrupt is generated every 32msec, is that correct?

     what I'm trying to figure out is how the time (in watchdog mode) is calculated using a 32768 Hz Xtal.

    Ref. the additional table I found: If SSel = 0 (SMCLK) and IS1 and IS0 = 00, how do they get 32msec?

     I was thinking 32768/32768 = 1sec (or 1000msec), this appears to be true if SSel = 1(ACLk).

     Completing the table from my origional post: SSel = 1, IS1 IS0 = 01 >>> 32768/8192 = 4

                                                                                                               10 >>> 32768/512 = 64

                                                                                                               11 >>> 32768/64 = 512

     ok, these don't match up with the table.  If I invert the results: 1/4 = 250 mSec

                                                                                                                  1/64= 15.6 msec

                                                                                                               1/512 = 1.95msec

    These are close to what is shown in the table.

     I'm not sure why I needed to invert the origional results.

     Now, what about: SSel = 0(SMCLK)  IS1 IS0 00 >>>>> 32768/32768 = 1 How do you get 32msec from that?

                                                                     01 >>>>> 32768/8192 = 4 How do you get 8msec from that?

                                                                      10 >>>>> 32768/512 = 64 How do you get 0.5msec from that?

                                                                       11 >>>>> 32768/64 = 512 How do you get 0.064msec from that?

     As you can tell I don't have a clue how these numbers were derived.

     Any help in deriving these numbers would be greatly appreciated.

    Also, could point me in the direction of the header file (#include ) which corresponds to the software. It wasn't there when I extracted the software.

    Thanks

  • 0 in reply to william hutt
    TI__Expert 7845 points

    I see where the confusion may be:

    1. Default SMCLK=800 Khz (see section 4.2 of the 1xx user's guide):
    http://www.ti.com/litv/pdf/slau049f

    In Watchdog mode default reset time is:
    32768/800000 ~ 40 ms (The WDTISx bits give the interval in Hz, so to get a time base, you have to reverse the formula: 32768/Clock Frequency)

    32 ms Reset time is assuming a 1.048576 Mhz DCO clock upon power up (which is the case in all devices except 1xx device family). That is why it is put as a ballpark number in the user's guide.

    2. If you are using a 32768 Hz crystal as your clock source for Watchdog (using SSEL bit) and a divider of 64 (using WDTISx bits), the reset will happen every:
    64/32768 = 1.9 ms

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