Hi,
I am using MSP430F5438A EVM, and want the system clock at 20 MHz. Following is the code snippet for the same. But due to some reasons it does not come out of the
do.. while loop checking the fault flags. What can be the reason and is there a way to have the system clock at 20 MHz. I want this clock rate for some other processing.
#include "msp430x54x.h"
#include "hal_pmm.h"
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
SetVCore(PMMCOREV_3); // Set VCore > 2.2 V for 20MHz clock
P1DIR |= BIT0; // P1.0 output
P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins
P11SEL |= 0x07; // P11.0,1,2 for debugging purposes.
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x1F00; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select DCO range 24MHz operation
UCSCTL2 = FLLD_1 + 610; // Set DCO Multiplier for 12MHz
// (N + 1) * FLLRef = Fdco
// (610 + 1) * 32768 = 20MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 20 MHz / 32,768 Hz = 625000 = MCLK cycles for DCO to settle
__delay_cycles(625000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
while(1)
{
P1OUT ^= BIT0; // Toggle P1.0
__delay_cycles(600000); // Delay
}
}
