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Using TimerB ch0 and ch1

PeterETT
Prodigy 115 points
Other Parts Discussed in Thread: MSP430F2618

Hi,

i am using MSP430F2618 and try to set up TimerB ch0 and ch1 to generate interrupts.

Only ch0 interrupt will occur. Why?

code:

void clock_TimerSetup( void ) {
 
 /* Set compare value */
    TBCCR0 = 32768;

 /* Set compare value channel 1*/
    TBCCR1 = 16384;
   
    // Compare mode, clear interrupt pending flag, disable interrupt
    TBCCTL0 = 0;
    TBCCTL1 = 0;
   
    /* ACLK,Divide by 1,Upmode, */
    TBCTL = TBSSEL_1 | ID_0 | MC_1 | TBCLR;

 
 TBCCTL0 |= CCIE;
 TBCCTL1 |= CCIE;
}

#pragma vector=TIMERB1_VECTOR
__interrupt void timerB1_ISR(void) {
 IO_TOGGLE_PORTPIN(4,0);
}

#pragma vector=TIMERB0_VECTOR
__interrupt void timerB_ISR(void) { 
 IO_TOGGLE_PORTPIN(4,1);
}

What am I doing wrong?

/Peter

  • 0
    Guru 58965 points

    timerB1_ISR() is shared with other interrupts from TimerB. You need to either test and clear individue flags or use TBIV to vector and automatically clear individue interrupts.

  • 0 in reply to old_cow_yellow
    Prodigy 115 points

    Thanks,

    so the TBCCR1 CCIFG is not cleared automatically when the ISR is executed?

    I have to access the TBIV register to clear the interrupt flag. Is this correct?

    /Peter

  • 0 in reply to PeterETT
    Guru 58965 points

    Correct.

    If you access TBIV, it tells you what the highest priority interrupt is and automatically clears the corresponding flag. (Lower priority flag, if any, remain set and will generate interrupt again after you finished servicing the highest one.)

    If you do not access TBIV, you can read the CCTRx registers to see if the CCIFG bit is set or not. But in this case, the flag is not automatically cleared. You can decide which one to service and clear by yourself.

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