5 Independent Timers in MSP430

Hi Sharwari,

you want to count external events and the have an interrupt if a certain count value is reached, would'nt you? And you need this 5 times, correct?

This should be no problem on first view, since the only thing you need to do is using a MSP430 device which has a TimerA or TimerB with at least 5 capture and compare interrupts (or use two timers with 5 capture/compare regsters in total (use the product selector and have a look at the timer details; CCR means campture/compare). You then write the max count value to the compare registers, confgure the correspondent I/Os as inputs (TAx or TBx) and the you need to configure the timer for capture and compare mode (refer to the users manual how to do this). At least you need to configure which event should be captured, the rising, falling or both edges of the inputs (TAx or TBx). Add the functinality needed to the timer interrupt service routine (maybe you schould use the samples code provided by TI as a starting point), enable the interrupts and start the timer. That's it! The correspondant interrupt will be handled on compare match.

Rgds
G**buster 

Hi,

in addition to my last post, and - since a bit of code says more than a thousand words - here is a pice of code extracted from the MSP430F54xx C sample code (msp430x54x_tb_03.c) provided by TI (pls rfer to http://www.ti.com/litv/zip/slac166j).

It shows the TimerB interrupt service routine. TimerB has only one interrupt vector but TBIV is used to generate 7 interrupt sources (related to the capture and compare registers).
For your application this means:
case2 is your first interrupt source
case4 is your second interrupt source
...
case10 is your fifth interrupt source

Hope this helps.
Rgds
G**buster

// Timer_B7 Interrupt Vector (TBIV) handler
#pragma vector=TIMERB1_VECTOR
__interrupt void TIMERB1_ISR(void)
{
  /* Any access, read or write, of the TBIV register automatically resets the
  highest "pending" interrupt flag. */
  switch( __even_in_range(TBIV,14) )
  {
    case  0: break;                          // No interrupt
    case  2: break;                          // CCR1 not used
    case  4: break;                          // CCR2 not used
    case  6: break;                          // CCR3 not used
    case  8: break;                          // CCR4 not used
    case 10: break;                          // CCR5 not used
    case 12: break;                          // CCR6 not used
    case 14: P1OUT ^= 0x01;                  // overflow
            break;
    default: break;
  }
}