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Bandwidth of SPI

JP2465
Intellectual 385 points

 Hello,

Easy question : I am currently evaluating the new family of MSP430 : the MSP430x5xx and I wish to know whish is the practical bandwidth of the SPI channels.

 

Is this data somewhere I have not found? Please point me on the info.

Thanks !

 

  • 0
    TI__Mastermind 24315 points

    JP,

     For the MSP430x5xx series, the USCI serial module retains essentially the same functionality and speeds as the previous series MSP430.

    Per page 16-11 of the 2xx Guide, The maximum bit clock that can be generated in master mode is BRCLK. Link: http://focus.ti.com/lit/ug/slau144e/slau144e.pdf

    Now you may also be interested in this app note, which enumerates the changes from previous MSP430 families to the 5xx series: http://focus.ti.com/lit/an/slaa396/slaa396.pdf

    EDIT: This is also reflected on page 432 of the 5xx User's Guide: http://focus.ti.com/lit/ug/slau208/slau208.pdf

  • 0 in reply to Brandon08
    TI__Expert 3325 points

    Brandon,

    Is it safe to say that you can run the SPI at the max 25MHz in both master and slave configurations?

    thanks -emil

  • 0 in reply to Emil2318
    TI__Mastermind 24315 points

    Emil said:

    Brandon,

    Is it safe to say that you can run the SPI at the max 25MHz in both master and slave configurations?

    thanks -emil

     

    Emil,

    For the SPI Master: yes. The 5xx series can transmit at 25 MHz provided the system clock is configured at 25MHz.

    For the SPI Slave: sort of. The Baud Rate depends on the Master's Clk, but in case the CPU speed is 25 Mhz and the master clock is 25Mhz, with a polling scheme, the slave will have very few clock cycles to process the data it receives, before the next byte comes in.  All in all you have to take processing overhead on the slave's end into account with the SPI baud rate.

  • 0 in reply to Brandon08
    TI__Expert 3325 points

    Thanks Brandon,

    The master will be driving an 18MHz clock to the F5xx and the data will be bursty, so cycles to process the messages should not be a problem (probably interrupt based).  I just wanted to make sure there are no synchronization problems with the SPI running at close to the system clock and there is no limitation such a 1/2 or 1/4 the system clock.

    It looks like it's possible to run the SPI at 18MHz provided the core clock is 18MHz or greater.

    regards -emil

  • 0 in reply to Emil2318
    TI__Mastermind 24315 points

    Emil,

    My previous post regarding this topic was actually a little too optimistic. Your question jogged my memory about a previous discussion I had with the factory apps:

    I found the equation for maximum UCxCLK. Yes, you could apply the system clock, but it's too fast to be useful. I found the maximum frequency for SPI operation in the F2619 datasheet:

    f_UCxCLK = 1 / (2*t) where t is greater than the largest value of either (t_valid,MO + t_setup,SI) or (t_setup,MI + t_valid,SO)

    Here are the USCI specs on the F5438, resulting in the following:

    t_valid,MO = 25 ns (max)
    t_setup,SI  = 20 ns (min)
    t_setup,MI  = 65 ns (min)
    t_valid,SO  = 62 ns (max)

    t is equal to the larger of 45 ns or 127 ns, so t = 127 ns => 1/(2*127ns) =  ~4 MHz.

    This a WORST CASE analysis, so I guess it makes sense that you saw the SPI communication work at 6 MHz on your desk, but a 13 MHz bit rate (or greater) is pretty much out of the question.

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