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MSP430G2553 and prescaler problem

Gianfranco Costamagna
Prodigy 30 points

Hi everybody I have to implement a WSN with an msp430.


The application is low power, so what I do is to wake up once a minute, listen for messages, go to sleep.


I thought to give a "window" to every sensor, so no collisions are possible.

My problem is that to keep them in sync every sensor need to receive a "beacon" and to reset his counter (TAR register) in order to wake up next time in sync with the node.

So what I do is to receive bacon and set tar to a value like "maximum-K*mac_address_sensor"

K is the window's length.

I need this formula since every sensor sends the beacon in its window, so I need to wake up earlier (corresponding to the window 0).

My problem is that I read something about a prescaler error, when I write TAR next increment will be based on the prescaler status and not when I want.

How can I keep them in sync?

thanks

  • 0
    Guru 227245 points

    Yes, when you write to TAR, then thsi changes TAR only, and not the prescaler. It has no meaning when the prescaler is deactivated (ID_1 is used).

    If you set the TACLR bit, ti will clear both, TAR an dht eprescaler.

    So the solution is simple: use the formula k*mac_address_sensor and write this to CCR0. And reset TAR when the beacon comes in.

    So the interrupt is triggered by TACCR0 compare and not by TAR overflow. This has the additional advantage of being a separate interrupt vector and you do not need to clear the IFG bit - it is done by hardware for CCR0, as soon as the ISR starts.

  • 0 in reply to Jens-Michael Gross
    Guru 58965 points

    The behavior of a Timer stays the same whether you (a) use a clock of a certain frequency and divide it with a prescaler, or (b) use a clock which is slower by the same factor to begin with.

  • 0 in reply to old_cow_yellow
    Guru 227245 points

    old_cow_yellow said:
    The behavior of a Timer stays the same whether you (a) use a clock of a certain frequency and divide it with a prescaler, or (b) use a clock which is slower by the same factor to begin with.

    Sorry, no. Not if you write to TAR register directly. Since this write will not set the prescaler back to 0, so it might worst case increment again one clock cycle later even though you have a /8 prescaler and expect it to increment in 8 clock cycles.

    However, I agree that the difference is uimportant if the event that triggered your attempt to reset the timer was cause dby teh very same timer (and therefore synchroneous to the scaled or not timer tick).
    But if it is an external event that made you reset the timer, a high clock with prescaler behaves differently than a slow clock without prescaler. In terms of when exactly the timer will timeout after you cleared it.

  • 0 in reply to Jens-Michael Gross
    Guru 58965 points

    I disagree. When you change TAR, TAR will change to the new value in either case. But it will still "count" at the original clock edge of the slower clock or the overflow of the prescalor.

    But if you CLR the counter, there is a slight difference. In the case of the slower clock, its phase will not change. In the case of the prescalor divided clock, the phase will change.

  • 0 in reply to old_cow_yellow
    Guru 227245 points

    old_cow_yellow said:
    But if you CLR the counter, there is a slight difference.

    Well, you're right. When you clear the counter, it will tick n clock pulses after you cleared it (whether there was a prescaler [n>1] or not [n=1]). If you just write to TAR, then it will tick when the scaled-down frequency would have ticked anyway, keeping the pace.
    So if you use a prescaler, you muse chose your method based on application. Do you want the timer to count from the moment you clear it with highest precision (not caring for any previous timing) or do you want it to continue ticking with the old pace.

    However, in most cases where you manually clear it instead of lettign it simply overflow (up or cont mode), you don't care for the pace but want a delay from the moment of clearing. Which requires clearing the prescalers if you use a scaled-down clock - or you lose precision.

  • 0 in reply to Jens-Michael Gross
    Guru 58965 points

    Case 1: Clock = 8MHz / 8

    Right after CLR, TAR = 0

    0.875+ to 1 usec later, TAR = 1

    Each 1 usec there after, TAR += 1

    Right after loading TAR, TAR = n

    0.000+ to 1 usec later, TAR = n+1

    Each 1 usec there after, TAR += 1

     

    Case 2  Clcok = 1MHz

    0.000+ to 1 usec later, TAR = 1

    Each 1 usec there after, TAR += 1

    Right after loading TAR, TAR = n

    0.000+ to 1 usec later, TAR = n+1

    Each 1 usec there after, TAR += 1

     

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