MCU with 16 byte UART FIFO buffer

Hi Kumar,

The MSP430 does not have UART FIFOs, but the DMA controller available in many MSP430 models can give you nearly the same capability.

The Stellaris ARM Cortex MCUs from TI do provide UARTs with 16-byte FIFO.

Jeff

Sorry but this is huge missing. Even with the MSP430F67xx series, they provide 4 UART (eUSCI) modules which is good but non of them has FIFO. 

I have an application which needs 400us to complete some filtering inside ADC interrupt by using all DMA channels which is already very limited (3 only). 

At 9600 baud rate, each byte receiving is around 1ms. Practically, it is not possible to receive bytes at higher baud rates because MSP430 UARTs don't have FIFO.

BasePointer said:

I have an application which needs 400us to complete some filtering inside ADC interrupt by using all DMA channels which is already very limited (3 only). 

Maybe you picked the wrong processor for your job.

FIFO means additional power consumption. Not much, but...

If you don't have the time to fetch incoming data when it arrives (or at least within the next 10 bit cycles), then use DMA to put it into a buffer. If you then don't have enough DMA lines, pic an MSP wiht more than the three you already have. (there are MSPs with 8). If this still won't be enough, get a PC with some PCI-cards with as many FIFOs as you need. :)

You can't have everything at once: much processing power, high communications capabilities and still ultra-low power consumption.

Also, spending 400µs for filtering inside the ADC interrupt is simply a bad software design. You shouldn't do anything time-consuming inside an interrupt. Never. It contradicts the meaning of interrupt. You're effectively spawning a parallel thread and block other interrupts during its runtime.

Hi Jens-Michael,

See that the MSP used has 7 channel ADC and each is 24bit, high speed! You have to process all these raw data in real time. 400uS is mostly written in assembly and designed very well to increase efficiency by using multiply-accumulate module, all DMAs, and it eats only 35% of whole MCU. This is nothing. But it is not possible to communicate at baud rates higher than 9600. Simple 4 bytes FIFO could multiply the speed by 4. This is not because of my "not well designed" software. This is because of "not well designed" MSP430 uart module. 4byte fifo wouldn't increase the power consumption, especially simply you could enable or disable it. Also "Ultra low power consumption" is just marketing. It is not valid anymore. Everybody has similar. It was maybe 5 years ago.

BasePointer said:

But it is not possible to communicate at baud rates higher than 9600.

Indeed. Because you are putting data processing which takes 35% of whole CPU power in the IRQ. This is bad design by definition in case application needs to process more IRQ's than this one "data processing IRQ".

BasePointer said:

Simple 4 bytes FIFO could multiply the speed by 4.

Out of UART DMA capability you can make 512 byte or even bigger FIFO. What's the problem?

Ilmars said:

Indeed. Because you are putting data processing which takes 35% of whole CPU power in the IRQ. This is bad design by definition in case application needs to process more IRQ's than this one "data processing IRQ".

What is the other way doing it? This is the way suggested by TI.

Ilmars said:

Out of UART DMA capability you can make 512 byte or even bigger FIFO. What's the problem?

Number 2: Even there was DMA channel available for UART reception, practically it is not possible to use DMA to implement state machine required by communication protocols. No way to handle parity or frame errors, intercharacter-timeouts etc.

BasePointer said:

What is the other way doing it? 

Given fact that you have 65% CPU power left, CPU may have plenty of time to handle data processing out of IRQ. To say something, more info about application and it's constraints needed. 

BasePointer said:

This is the way suggested by TI.

[..] filtering as per TI application note.

Very interesting.. May I ask you to tell which TI design suggestion and/or application note you are talking about? Where we can find it to read?

http://www.ti.com/lit/an/slaa228/slaa228.pdf

Now I see... This application note is just FIR filtering example, done easy way to show just FIR filtering, nothing more. Definitely this is not example about how to do proper multitasking.

Solution is: superloop. You don't even need DMA for UART, just software circular TX/RX buffers. IRQ routines does very little, data processing like FIR filtering is done in main loop, serial i/o through buffers too.

BasePointer said:

Sorry but this is huge missing

This is why there is more than just one microcontroller in the world!

If it's a Big Deal for your application, that rather suggests that the MSP430 is not a good choice for your application.

Discussing whether MSP430 is good for my application is pointless. All MCUs have strength and weakness. Current UART design of MSP430 series is the one of its weaknesses. And there is no logical reason not to have a few bytes FIFO. TI simply should improve it with the new series.

BasePointer said:

Discussing whether MSP430 is good for my application is pointless.

Yes. Because it's fine for your application as it is even with UART having no FIFO :D

BasePointer said:

See that the MSP used has 7 channel ADC and each is 24bit, high speed!

BasePointer said:

This is because of "not well designed" MSP430 uart module.