IO Interrupt response time for MSP430?

AFAIK, it's 20ns minimum pulse time, specified as t(int); however I can only find the number in a few of the datasheets I surveyed even though t(int) is referenced in almost all of them... not sure why that's the case.

Tony

Tony,

It is the same for me. In G2302 datasheet if I search SLAS723F there are eight occurrences. The last few of the hits are about POR/brown-out time, but for IO port pulse reset time there is no information.

Could you tell me in which datasheets did you find the value?

And could any TI people follow up on this?

 

Matt

Tony,

I checked in the three documents you referred and it is true. Hope some TI people could come up with the figures for G-value device, particularly G2302.

 

Matt

Hi guys,
          I got intrigued by the topic and looked at the datasheets myself. Indeed the F2350 datasheet says that t(int) is 20ns where t(int) is:

msp430f2350.pdf page 21 said:

Port P1, P2: P1.x to P2.x, External trigger pulse width to set interrupt flag.

with a note:

msp430f2350.pdf page 21 said:

An external signal sets the interrupt flag every time the minimum interrupt pulse width t(int) is met. It may be set with trigger signals shorter than t(int)

But then pages 44-52 show diagrams (and similar diagrams are shown for input ports of G2553 in pages 42-54 in msp430g2553.pdf) where PxIFG flag is clearly set by a flip-flop which also generates the interrupt (PxIRQ).

That flip-flop must be clocked by MCLK and so the minimum external pulse width to guarantee the flip-flop to change must be governed by the period of MCLK. So if you're running at 1MHz then that's 1us. 20ns would require 50MHz clock.

I wouldn't mind if the 20ns was meant to be the reaction time of the input Schmitt trigger but I am a bit puzzled when it's defined as it is with a flip flop as well and I remain puzzled.

Well, lets wait for JMG to come in and clarify things :).

Hi Arturs,

Arturs Elksnis said:

But then pages 44-52 show diagrams (and similar diagrams are shown for input ports of G2553 in pages 42-54 in msp430g2553.pdf) where PxIFG flag is clearly set by a flip-flop which also generates the interrupt (PxIRQ).

Looking over the aforementioned part in the datasheet, I don't think that's a synchronous flip flop as I don't see a clock line; it looks like an S latch with enable, the output of which feeds the interrupt flag for the pin. So the 20ns is likely the recovery and removal timing for the latch.

Tony

Arturs Elksnis said:

That flip-flop must be clocked by MCLK

No, it isn't. Else you wouldn't get any interrupt sif the CPU is in LPM (MCLK off). Tdigital circuitry works as fast as it can. Where specified, these 20ns are guaranteed to trigger an interrupt, shorter periods may or may not trigger. For the G series, there is no expplicit value specified, but you can calculate a safe value from the general digital I/O port description.

Keep in mind that CMOS circuitry works slower for lower VCC. So it's likely that with VCC=3.6V, the required minimum pulse width for an interrutp may be much shorter than with VCC=2.2V. There simply is no such thing as "the" value.

Arturs Elksnis said:

Well, lets wait for JMG to come in and clarify things :).

I don't have more information than you. For me too, the datasheets are the only source.  In most cases, I can only do some (maybe somewhat sophisticated) guesses by concatenating different information that is already available. Luckily, I haven't proved wrong too often (would be bad for my reputation) :)

JMG,

JMG said:

No, it isn't. Else you wouldn't get any interrupt sif the CPU is in LPM (MCLK off).

I agree. If using VLOCLK in LMP3 the VLO frequency is only at the order of 12KHz. If the port’s interrupt detection is synchronous to the master clock then it would really require 83.3μs pulse to trigger an interrupt.

I wonder if TI people can provide a definitive answer to conclude this thread?

 

Matt

Hi all,

Matt Shira said:

I agree. If using VLOCLK in LMP3 the VLO frequency is only at the order of 12KHz. If the port’s interrupt detection is synchronous to the master clock then it would really require 83.3μs pulse to trigger an interrupt.

Like I mentioned previously, it looks like the schmitt trigger feeds an S-latch which in terms feeds the interrupt flag/line, so I presume the pulse timing would be the aggregate response times of the two gates, which with modern CMOS process should easily achieve the 20ns minimum.

Of course I also think it nice to get an official response from TI :)

Tony

Matt Shira said:

If using VLOCLK in LMP3 the VLO frequency is only at the order of 12KHz.

In all LPMs, MCLK is OFF. Completely. No MCLK at all. CPU isn't just idling, it doesn't have a clock and is frozen in its current state. And so were the interrupts if they were synchronized with it.

Jens,

Here is the definitions of LPMs from TI’s msp430g2302.h:

TI msp430g2302.h said:

/************************************************************

* STATUS REGISTER BITS

************************************************************/

#define C                      (0x0001)

#define Z                      (0x0002)

#define N                      (0x0004)

#define V                      (0x0100)

#define GIE                    (0x0008)

#define CPUOFF                 (0x0010)

#define OSCOFF                 (0x0020)

#define SCG0                   (0x0040)

#define SCG1                   (0x0080)

/* Low Power Modes coded with Bits 4-7 in SR */

 

#ifdef __ASM_HEADER__ /* Begin #defines for assembler */

#define LPM0                   (CPUOFF)

#define LPM1                   (SCG0+CPUOFF)

#define LPM2                   (SCG1+CPUOFF)

#define LPM3                   (SCG1+SCG0+CPUOFF)

#define LPM4                   (SCG1+SCG0+OSCOFF+CPUOFF)

The LMP0 does not put off either SCG0 or SCG1, but according to MSP430x2xx Family User's Guide Table 3-1. Description of Status Register Bits:

1. SCG1 System clock generator 1. When set, turns off the SMCLK.
2. SCG0 System clock generator 0. When set, turns off the DCO dc generator, if DCOCLK is not used for MCLK or SMCLK.
3. CPUOFF CPU off. When set, turns off the CPU.

So do you mean that even if ONLY CPUOFF is set the MCLK is still completely off?

 

Matt

Jens,

This is true for "CPUOFF" bit. Thanks!

Matt