MIDI out of the UART of an MSP430 - How do I get the 31,250 bps frequency?

Take a calculator, add 31250 and again and again until the intermediate result is a frequency you like.

A very common one is 1MHz that divides nicely by 64 into 31250. That's why MIDI uses this rather odd frequency :)

If you have a base frequency of 1MHz (factory calibrated or better manually calibrated DCO or even a 1MHz crystal) for SMCLK, teh USART or USCI module will take it with  a divider of 64 for exact 31250Bd. For higher crystal frequency, increase the divider accordingly.

Well, I'm using the classic 12MHz crystal, but I'm sure it would have to be tuned - as the starting frequency goes up the resulting accuracy would go down right? This crystal depends quite a bit on the loading caps (and maybe other things - learned this the hard way). So even if I did try to tweak the crystal loading close with off the shelf components, I probably couldn't control that in production... or is MIDI somewhat forgiving?  The other crystal is 32,768 Hz, wonder if that's close enough? And since I've already got 2 crystals on the CC430, I can add more??? Where?

Thanks!

Wait, silly question... What's my other crystal for anyway (32,768)?  Maybe swap it out for a 1MHz?  Basically if you had a Chronos Watch, how would you approach it?

Can (or should) I use the Radio crystal (12MHz), because the CC430 requires a "The Unified Clock System (UCS) module includes support for a 32768-Hz watch crystal oscillator."  So instead, use the radio 12Mhz crystal and div down further? If the error on my RF spectrum measurement is proportional to my oscillator error, then I'm very close! Another though is to set the CPU to 1MHz (like low power).... If so, how do I use the CPU clock or divide down as needed?

Good to know! So replace my 32768 crystal with say a 1 MHz (or less maybe)? The CC430 doesn't support USB, but will my other I2C port still work? 

I'm thinking if we divide down the 26MHz crystal from the radio, the result might be out of tolerance for MIDI. However, I'm quite close to the 915MHz, so maybe worth a try. 

Thanks again,

John

John DAmours said:

I'm thinking if we divide down the 26MHz crystal from the radio, the result might be out of tolerance for MIDI.

The CC crystal has to be 26MHz. 27MHz at max, but it is you who picks the crystal frequency. And a 27MHz crystal gives 27MHz and a 26MHz crystal gives 26MHz and not something random. This is why crystals are used.
If you assign XT2/RF_X to SMCLK and use a SMCLK divider of 2 (DIVS_1), you have 13MHz SMCLK. This gives a clean and pecise factor of 13*32 = 416 for the USCI baudrate divider, resulting in 26MHZ/2/416=31250Bd. As exact as your crystal is. You can't get a more precise, exact and stable frequency than what a properly attached crystal gives.

(p.s.: there was a mistake in my previous posts. The divider for 1MHz is of course 32 and not 64)

FYI, the 32768 Hz crystal on the Chrono is used as a low power, accurate time source for the watch function of the Chrono. If you ran the watch strictly off of the 12 MHz clock, the battery life would be much reduced. If your design does not need accurate timing you can use the on chip low power oscillator for a slow clock.

According to the CC430 data sheet, XT1 is striclty for a low frequency, low power crystal, but has a bypass mode that accepts a square wave signal (like from a crystal oscillator) on one pin. Clock speed is speced per a schmit triggered input, but I could not find anything in the data sheet on input pin timing.  The second crystal input is for the RF section, but is also connected to the unified clock system. So Jen's suggestion of using a divided down RF clock would work. If you are using SimpliciTI to send data on the RF section, you will need to make some minor adjustments to the BSP code, since SimpliciTI is using 12MHz for MCLK.

Power will be a concern (eventually). MIDI spec is +/- 1% so do you think the LPO will meet this tolerance?  

If all else fails, I'll tie the XT2CLK to one of the others (ACLK, MCLK, or SMCLK) but I'm already using the SMCLK for SPI on the other port. So it has to be one of the other 2 (ACLK or MCLK) correct? 

Thanks, this is grueling... Anyone know the code I would use to connect up XT2CLK to, say, ACLK, then out a port?

John

Jens,

I was using Dunn's calculator last night and came up with 832 divide. But is that baud rate or bit rate (remember, MIDI is bit rate)?

So much to learn, but these posts definitely help. Thanks again everyone. 

Oh funny you noticed the 5V thing. I was concerned that if the CPU output goes high (3V) then there would still be a loop current and wouldn't turn off (from the 5V supply I have). Many PIC diagrams don't show this but it bugged me enough to put a fast switching FET in there. There doesn't seem to be any rules regarding the 5V (probably would work with 3V), but I'm not taking that chance.

Thanks for noticing that, it's subtle, good eye!

John

The MIDI spec also requires isolation on the input, I believe. Most designs use an opto-isolator, and show a dedicated buffer or transistor for the output. So you can use that for any 3.3V to 5V translation .

This doesn't seem to be sourcing the correct clock. My pulse width on a scope is about 6ms and needs to be more like 32us (for 31,250 MIDI clock).

Approach was to use XT2 (26Mhz) on SMCLK, (based on sample code). Any help or ideas would be great thanks!

void main(void)

{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT

PMAPPWD = 0x02D52; // Get write-access to port mapping regs
P2MAP6 = PM_UCA0RXD; // Map UCA0RXD output to P2.6
P2MAP7 = PM_UCA0TXD; // Map UCA0TXD output to P2.7
PMAPPWD = 0; // Lock port mapping registers

P2DIR |= BIT7; // Set P2.7 as TX output
P2SEL |= BIT6 + BIT7; // Select P2.6 & P2.7 to UART function

// Set up Green LED
P1OUT &= ~BIT0;
P1DIR |= BIT0;

UCA0CTL1 |= UCSWRST; // **Put state machine in reset**
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCSCTL4 |= SELS__XT2CLK; // SMCLK=XT2

UCSCTL6 &= ~XT2OFF; // Enable XT2 (26MHz)

UCSCTL5 |= DIVS_2;
UCA0BR0 = 0x32; // 64/2
UCA0BR1 = 3; //

// UCA0MCTL = 0; // No modulation
// UCA0MCTL = UCBRS_0 + UCBRF_13 + UCOS16; // Modln UCBRSx=0, UCBRFx=0, over sampling
UCA0CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCA0IE |= UCRXIE; // Enable USCI_A0 RX interrupt

while (1)
{
while (!(UCA0IFG&UCTXIFG)); // USCI_A0 TX buffer ready?
UCA0TXBUF = 0xAA; // send 1010 1010 data
P1OUT ^= BIT0; // Toggle LED
}
}

First, why did you start a second thread? I answered there.

However, here are almost the same answers again:

John DAmours said:

UCSCTL5 |= DIVS_2;

John DAmours said:

UCA0BR0 = 0x32; // 64/2
UCA0BR1 = 3; //

Sorry, I was trying a different angle for a truly different question, and the results were also different. The second approach wasn't really asking about the dividers, it was about connecting the 26MHz clock up and possible reasons why my code for this didn't work and you helped explain possible scenarios quite well. The answer was that the radio crystal is picky (and more accurately had to be handled with care regarding possible faults in working the UART this way). In the end, everyone's input helped tremendously and saved me from having to find a 31.25K crystal (which are not readily available).

Bottom line, it's working. Thanks again!

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