In the code to increment and decrement core voltage, the conditions on the delay for SVM to settle are inconsistent. Two are:
//Wait until high side, low side settled
while (((HWREGB(baseAddress + OFS_PMMIFG) & SVSMLDLYIFG) == 0) &&
((HWREGB(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0)) ;
while one is:
//Wait until SVM high side and SVM low side is settled
while ((HWREGB(baseAddress + OFS_PMMIFG) & SVSMHDLYIFG) == 0 ||
(HWREGB(baseAddress + OFS_PMMIFG) & SVSMLDLYIFG) == 0) ;
From reading the user's guide and the example code there, I believe the latter is correct. The code has been unchanged from driverlib 1.10 through 1.25.