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ADC12 "autocalibration"

Argail
Expert 2080 points

I was interrogating me on the possibility to autocalibrate the ADC12.

This by enabling the internal Vref, putting it on output (VeREF+ pin) and measuring it through ADC input (should read 0xFFFF), the same thing could be done for VREF-, then slope and offset could be calculated.

Could it give good results for the circuit using VREF?

I made some test measuring the internal VREF and it gives me wrong value, I measure 2470 (after NADC conversion and TLV correction) but should have 2500, I'm using 2.5V for this test and the PZ100USB board with F6638 uC (same results with custom boards).

But I don't know if I'm mistaking during conversion, or putting VREF in some an ADC loop (internal - external - input) will break the measurement.

Best regards

  • 0
    Guru 227245 points

    Two things: first, calibrating a reference by itself isn't a good idea. Gain error (slope) is many caused by the reference itself, not by the ADC. Then of course an offset error could be measured this way, but only a negative offset, because for a positive offset, the result is in saturation (0x0fff) already.

    Argail said:
    I measure 2470 (after NADC conversion and TLV correction) but should have 2500

    This is 1.2% error and outside the 1% reference precision. But the ADC as well as teh reference has some influencing factors.

    What is the ADC12CLK you use? For >2.7MHz, the REFOUT bit must be set to minimize the conversion error, which is several LSB. See the 12 bi tADC linerarity parameters table in the device datasheet.

    What do you get without NADC conversion and TLV correction?

  • 0 in reply to Jens-Michael Gross
    Expert 2080 points

    Thank you for the advice concerning the "calibration" wrong idea;)

    Concerning my problem in fact it's a nood mistake. I've tested my ADC function without REFOUT enabled. I had a look to the datasheet in order to see a resistive element to calculate the tau for the external 10u+100n, but didn't see anything, so I assume the tSETTLE (SLAS566B p72) defined was OK as REFOUT=1 and 10u+100n is the recommended circuit. Where should I find the information to calculate a theoretical settling time?

    When enabling it, it requires much longer time (10 times ~1ms) to allow VREF to settle. With a longer waiting time between REFON and ADC12SC the mearure seems good....

    Setting REFOUT is interresting to improve the conversion accuracy. It seems possible to have a wait loop during program init to charge the capacitors, after that 75us for tSETTLE is sufficient. The concern is I use 1.5V and 2.5V VREF, the behaviour of the external voltage will be a problem.

    I'm using ADC12OSC/3 and the VREF is measured at 2.50V.

     

  • 0 in reply to Argail
    Guru 227245 points

    Argail said:
    Where should I find the information to calculate a theoretical settling time?

    I don't know. Well, capacitance on VREF+ is known and with the specified output current, the charge tiem ould be calculated.

    Another approach is to measure VCC/2 against the reference. Initialy, with a low reference, the readings are too high and finally settle (does not change anymore). Then the reference should be stable (assuming that VCC is stable and doesn't change, of course). However, this won't work for CXX=3.3V and 1.5V reference.

    If current consumption is no problem, I recomment using an external reference anyway. I use the TS431BCX, a 0.5% 2.495V shunt regulator. It's minimum load current of 0.5mA is quite high, but the regulated voltage is very stable across a total load of 1-100mA.

  • 0 in reply to Jens-Michael Gross
    Expert 2080 points

    I've tried the way to use the current to calculate charging time, in this way I looked at Iref+ described in the datasheet. In order to know if those values are meaningfull, I've made some measurement with ADC12SR=1 and 0 and this do not changed the settling time.

    But this is the result of only some preliminar tests, take it "as it is".

    I didn't have the budget to use a TS431BCX (current, money and board room:))

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