MSP430 Port Schematics - What is the use of this link?

LaunchRed

Prodigy 240 points

Other Parts Discussed in Thread: MSP430G2553

http://www.ti.com/lit/ds/symlink/msp430g2553.pdf (SLAS735G-APRIL 2011-REVISED AUGUST 2012)

page 56:

What is the usefulness of such a link in green? It exists on all ports, the P3.0 was used because it is the simplest.

over 13 years ago

0 Arturs Elksnis over 13 years ago

Intellectual 715 points

It looks like when PxSEL2 = 1 and PxSEL = 0 then it has the pull up/down resistor enabled and if the input is 1 then it pulls it down and when input is 0 then it pulls it up.

In http://www.ti.com/lit/ug/slau144i/slau144i.pdf on page 337 there's a table that says:

PxSEL2 PxSEL Pin Function
0 0 I/O function is selected.
0 1 Primary peripheral module function is selected.
1 0 Reserved. See device-specific data sheet.
1 1 Secondary peripheral module function is selected.

So our mode when PxSEL2 = 1 and PxSEL = 0 is a reserved mode and the device specific data sheet only shows the picture that you've already posted. Also the output buffer will be disabled in this special mode.

My guess is two possibilities:

1) The implementation of the output buffer is such that it's desirable to have the same Voltage levels on either side when it's disabled.

2) If PxDIR = 1 (so port is set as output) then the output buffer would see levels that come from MUX and MUX would be providing levels that come on it's 2nd input. It looks like 2nd input is disconnected but then again it might actually be providing some test levels when testing the IC in the factory and then the link in question would allow verifying that test levels are correct because they would be routed directly to PxIN while the actual physical output of the device would be disconnected.

0 Avi Chami1 over 13 years ago in reply to Arturs Elksnis

Mastermind 7395 points

My impression is that it is a feedback which is part of the bus keeper logic. That means, if the input goes to a floating or high impedance status, that logic keeps the input at its last driven value.

0 LaunchRed over 13 years ago in reply to Avi Chami1

Prodigy 240 points

It is not yet clear. Someone who have sure in reply?

0 Jens-Michael Gross over 13 years ago

Guru 227245 points

I too reported this strange 'shortcut' soem tiem ago as a possible bug in teh documentation.

I too suspected it to be a misdrawn bus-keeper logic, but on other port pins there is a bus keeper (here is none because of the pinosc feature. i think) and still this strange connection.
So I don't know what its meaning is. From a plain schematics view, it must be an error, as it maks the output of the module fighting the output of the input.

0 LaunchRed over 13 years ago in reply to Jens-Michael Gross

Prodigy 240 points

Where report bugs?

0 Jens-Michael Gross over 13 years ago in reply to LaunchRed

Guru 227245 points

On older documents, there was a feedback link. In newer ones it has been removed. However, this specific issue has already been reported by me.

**Attention** This is a public forum

MSP low-power microcontrollers

MSP low-power microcontroller forum

MSP430 Port Schematics - What is the use of this link?