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SD card query

Aamir Ali
Expert 2525 points
Other Parts Discussed in Thread: CSD

Hi,

I am using SDHC card, class 4 writing with SPI protocol.

1. Can I write/read single byte also or it is fixed at 512 bytes packet.

2. What is max freq I can achieve. I read 25Mhz. Also I read that for SDHC min read/write tranfer rate is 4MB/sec. Which one should be followed.

  • 0
    Guru 227245 points

    Copy from our private conversation:

    Question 1 cannot be answered authoritatively. It depends on the card. When you read the CSD register (Card Specific Data), it will tell you how large the segment size is and whether it is allowed to write partially segments.
    But on these cards, the address you give when writing, is no longer a linear byte address but a segmetn address (so you can give a >4GB address location with the 32 bit address field), and I think (I didn'T read the standard) that this means you can only write full segments or at least have to start writing at the beginning of  asegment (even if you don't write full size).

    On standard SD cards, some allow you writing a single byte anywhere on the 4GB address range. Then card controller will then read the whole segment into a buffer, apply your changed byte(s), erase it, and write it back. SO even if oyu only write a byte, it is still a full segment erase/write cycle internally. If the CSD tells you that partially writes are not supported, then you'll have to read the whole segment first and then write it back after changing the byte(s). It depends on the card.

    For the second question, yes, the maximum SPI clock frequency you may apply is 25MHz. SDHC cards in parallel mode support higher frequencies, but AFAIK not for SPI. One reason might be that at higher speeds, the chance of a transmission error increases, and in SPI mode, there is no CRC to detect it.
    The specified minimum transfer rate measn that the card controller can read and write at least 4MB/s (which would,  as you noticed, >32MHz clock). However, in parallel mode, 4 bits are transferred in parallel, and also the clock rates can (depeding on card class) be higher. How high is also provided through CSD register.
    But using 4-bit parallel mode makes no sense on an MSP. To do it, you'd have to do bit-banging for setting the four data lines, then generate a clock, and all in software. This would take much more than 8 MCLK cycles per byte, and with SPICLK==MCLK, you can send one byte in 8 MCLK cycles using SPI.

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