What does microcontroller do when its powered on?

Any microcontroller needs a reset signal, sometimes it is external, sometimes it is internal (like the MSP POR). Upon a power up, during the reset signal the clock generator stabilizes until it gives a stable clock output. The procesor does nothing, since it is kept in reset.

The following things are done while POR is asserted:

• The RST/NMI pin is configured in the reset mode.
• I/O pins are switched to input mode as described in the Digital I/O chapter.
• Other peripheral modules and registers are initialized as described in their respective chapters in this
manual.
• Status register (SR) is reset.
• The watchdog timer powers up active in watchdog mode.
• Program counter (PC) is loaded with address contained at reset vector location (0FFFEh). If the reset
vectors content is 0FFFFh the device will be disabled for minimum power consumption.

When reset is deasserted, the microcontroller starts running from address found at the reset vector

You can find more details here: http://www.ti.com/lit/ug/slau144i/slau144i.pdf

What is Boot ROM? what it does upon power up?

Please refer to the document I posted earlier, it is called bootstrap loader

I wish to know where data segment is implemented? Is it in RAM or ROM/Flash? 

Our local variables are stored in stack which is implemented in RAM . 

static , global variables are stored in data segmented is it implemnted in RAM? Is it so ? If will it lose contents when power is turned off?

Heap is implemented in RAM or Flash?

If you have runtime data that is important to save, it can be stored on Flash for further retrieval.

The heap is a dynamic allocation area, and as such, cannot be allocated to Flash, as far as I know.

Variables by definition must be in RAM. If you want to initialize their values, those intialization values can be in the Flash.

Albert_83 said:

The following things are done while POR is asserted:

Also, there are diffferent stages of reset. Some modules are only initialized on POR, most are later, on PUC. Only after POR, the BSL entry sequence is checked. This happens already after the CPU has started executing the boot rom. Reading 0xfffe is the very last step.