MSP430F5438 reset problem

It's possible that something has change P7SEL to 0, so XIN/XOUT turned to I/O mode.
It can have several reasons, maybe a yet undetected software bug, a radiation fluke (unlikely but possible), whatever.

If your code doesn't notice that XT1 has ceased functioning, but still triggers the WDT, the device will not reset but also not work properly.

Possible solutions: don't trigger the WDT unless the XT1 driven part of the code has signalled that XT 1is still working (e.g. the ISR of an XT1-driven timer sets a flag, and the WDT is only triggered if the flag is set (and resets the flag then).

Or you enable the OSC fault NMI and force a reset of the device if this NMI ISR is called. So once XT1 fails to oscillate, the device will reset.

Note that ACLK, when driven from LF-XT1, will revert to REFO on the 5438, but SMCLK, when driven by XT1, will simply stop.

JMG,

When LF-XT1 has a fault condition (XT1LFOFFG), REFO almost always stands in for XT1.  Even for SMCLK and MCLK (UG 5.2.12).  The WDT, however, uses VLO instead of REFO under these conditions (UG 16.2.5).

So an XT1 fault cannot stop ACLK, SMCLK, or MCLK, even if they are supposed to be driven from XT1.  Neither can an XT1 fault stop the WDT when it is configured to use XT1.  In that case, the WDT Clock Fail-Safe feature uses VLO instead.  The timeout period is longer than expected, but the watchdog is still working and will still reset the device.

To the OP,

With XT1OFF = 0, the only way XT1 should stop oscillating is if (1) the circuit design isn't right or doesn't match the firmware configuration or (2) the P7SEL bits became clear or (3) the device attempted to operate outside of specifications.  (I'm ignoring true hardware failures.)

One suggestion related to #3 especially for battery powered applications is to set the SVSHMD bit in SVSMHCTL in the PMM.  This adds high-side supervision even when in LPM.  Strange things can happen if there is a divot on the supply voltage while the MCU is asleep.

   PMMCTL0_H = PMMPW_H;  // Unlock write access to the PMM registers.
   SVSMHCTL |= SVSHMD;   // Keep SVS active on high side even in LPMx
   PMMCTL0_H = 0;        // Lock write access to the PMM registers.

Jeff

JMG & Jeff

Thanks for your advices.

When I posted this question I thought there is no DC bias at XIN and XOUT because I checked 0V on those two pins with oscilloscope. But today I found another thing, those pins are not simply 0V. When I touch the probe of oscilloscope on the pin, those two pins are few micro-seconds high then fell down. (This phenomenon is found at XIN and XOUT pin only. And the waveform like below was appeared in my oscilloscope every time when I touched one of those two pins with probe.)

The peak voltage is 1~2V. (3.6V battery is connected to my board)

I can’t understand the meaning. I guess that DC bias is added to those pins but It is impossible to maintain the voltage by some reason (current shortage or …). Is it correct? If not, please let me know the reason.

sholee

Jeff Tenney said:

REFO almost always stands in for XT1.  Even for SMCLK and MCLK (UG 5.2.12)

About the strange peak on XIN: it may be that there is some charge building up at the pin by crosstalk or leakage currents, which is discharged as soon as the probe is connected through the probe input impedance. Note that  a crystal is a capacitor of its own.