Error in workbook Lab 3

Pawan Garg said:

BCSCTL2 |= SELM_3 + DIVM_3;
seems to be incorrect. This should source the CPU from VLOCLK as explained on page 3-10.

Well, yes and no.
SELM_3 switches the MCLK to LFXT1CLK signal. This signal can come form both, LFXT1 or VLO. The LFXT1Sx bit switche sbetween these two possible uses. Onpage 3-10, this bit is set and the VLO is unconditionally used to source LFXT1CLK.
If this bit is clear, VLO is used if the crystal is not available/not yet running. But if the crystal is there, the crystal signal is used.

If you open the users guide, you'll find a nice schematic right at the beginning of the Basic Clock Module chapter. it shows what comes form where and whcih bits switch between different options.

I agree that this is a bit confusing. It is partly caused by an attempted compatibility to the very limited (regardign the clock system) 1x family while trying to introduce some more features. On 5x family, all this has been improved to be way more straight.

I think the original poster either skipped a couple of pages in the workbook or they are missing from their printout.

The intention of Lab3 is to experiment with the clock system on the device. You must configure both BCSCTL2 and 3 to correctly set up the clock.

Section 1 runs the device on the VLO (starting on page 3-9). The clock set up code is:

BCSCTL3 |= LFXT1S_2;                 // selects the VLO as the low frequency clock
BCSCTL2 |= SELM_3 + DIVM_3;   // selects the low frequency clock divided by eight

So this setup configures the clock system to be sourced by the VLO/8

Section 2 runs the device on the crystal, if it has been installed (starting on page 3-13)

BCSCTL3 |= LFXT1S_0 + XCAP_3;  // selects the crystal as the low frequency clock and configures the crystal bypass capacitors
BCSCTL2 |= SELM_3 + DIVM_3;      // selects the low frequency clock divided by eight 

So this setup configures the clock system to be sourced by the crystal/8

 

Scott