如何通过外部晶振来校准内部DCO？

this is what I see:

regards

Gastón

Gaston_Melo_Arg said:

this is what I see:

Maybe Old Cow Yellow can help here.

Jens-Michael Gross said:

If you ionstall the chinese font, you'll see nice, beautiful chinese letters. Howeve,r it doesn't help understanding what this thread is about. I don't talk chinese.

mmmmmmmhhhhhh....just thinking.....if I don't understand and I don't speak chinese.....installing the chinese font would help me to.......???? help ??

regards

PD: don't write a letter this time.

regards

Gastón

Huang yuohm said:

        首先感谢您的帮助。本人在使用MSP430G2553 的时候，需要用到一个高精度的1Mhz以上的 时钟信号。发现2553的内部DCO误差太大，想通过计算外部晶振脉宽来校准DCO，请问可以实现吗？如何实现？或者有更好的建议？  在此谢过。

Google translate:

First, thank you for your help. I use MSP430G2553 need a precision 1Mhz clock signal.Found the 2553 internal DCO error too, want to calibrate the DCO by calculating external crystal pulse width can be achieved? How? Or is there a better suggestion? Thanked.

-JD

I am impressed by Google translate. I wish they had a "g-compiler".

J.D. said:

I use MSP430G2553 need a precision 1Mhz clock signal.Found the 2553 internal DCO error too, want to calibrate the DCO by calculating external crystal pulse width can be achieved?

A precision 1MHz clock signal is almost impossible with the G2553. It would require a 1MHz (or multiple) crystal. Which isn't supported by the G series clock system.
The DCO can only provide an average frequency as it only has a limited number of discrete frequencies and alternates between them.

Closest thing is a frequency locked loop (FLL) where the timer counts DCO clock cycles during a reference interval (a 32768Hz crystal) and adjusts the DCO up or down depending on the result. MPS540F4x and 5x families implement this in hardware.

For the G series, this is using TimerA0: DCO output is sourced into SMCLK. An external 32768Hz crystal is sourced into ACLK.  TImerA0 is configured to run in contmode from SMCLK. TACCR0 is set up for capture mode on CCI0B (which is internally connected to ACLK).
This way, on every 'tick' of the crystal, the current count of TimerA0 is captured into TA0CCR0. The difference between two captures gives the number of DCO ticks per 1/32768s interval. For 1MHz, this should be 30.51757813 (therefore alternating 30 and 31).
To increase precision, ACLK can be divided by 2 (or 4/8). Then the difference between two captures is the number of DCO ticks per 1/16384s. Which should be 61.035. A value of 61 would give a frequency of 999424Hz. However, this is only an average, unless in very rare cases where the DCO can 100% hit the desired frequency at the current VCC and temperature.

Keep in mind, that this means one interrupt every 61 DCO clock cycles. And therefore you only have 61 MCLK cycles (also running on DCO clock speed) to handle the interrupt and do something useful too.
Alternatively, you can adjust the DCO to 2/4/8MHz, using a /2(/4, /8) divider for SMCLK while MCLK runs on DCO speed.

I don't try to translate this using GoogleTranslate since I have no idea how Google will handle all those register names (and I cannot check the result)

Jens-Michael Gross said:

...I don't try to translate this using GoogleTranslate since I have no idea how Google will handle all those register names (and I cannot check the result)

I checked it. The register names are handled correctly (i.e. un-changed). However, your "30 and 31" are translated into the 30th and 31th day of the month. Perhaps you need to declare them as "volatile" ;)