This part touts an LFO that runs at 12 kHz for low power applications.
Why would using this clock result in lower power than using a
full-speed DCO clock, actively running 12,000 / 16,000,000 of the
time, and sleeping the rest?
--RY
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This part touts an LFO that runs at 12 kHz for low power applications.
Why would using this clock result in lower power than using a
full-speed DCO clock, actively running 12,000 / 16,000,000 of the
time, and sleeping the rest?
--RY
HI, from non linear law of cmos frequency-power dependence, LFO @12KHz consume less power than an active DCO @16MHz, the same is for cpu so the equation of power say running from LFO frequency both cpu and LFO consume little power at no computing performance, running full speed then sleeping consume more power on cpu and on DCO.
If running cpu on LFO meet computing need can save energy.
Also refer this wikipedia article or ask again if in doubt.
Hi Roberto,
Thank you for your help.
The relationship between power and frequency is linear. It is nonlinear in voltage (V). Are you alluding to the higher Vcc required at the higher DCO values? I believe you can run at 1.8V up to 6 MHz. So 12000/6000000.
Hi take care of difference from current drawn and power or energy drawn:
try refer this application note, where power consumption is analyzed can see LFO stby consume less than DCO stby.
Current is proportional to frequency. At least in theory. But power is current*Voltage, and higher frequencies require higher voltage (as Roberto was already pointing out).Randy Yates said:The relationship between power and frequency is linear.
But even with constant voltage (on maximum), the current is not 100% linear with frequency. You have losses by HF effects that do not scale linearly with frequency. So half the frequency is actually a tiny little less than half the current. THis is, however, negligible in the very most situations.
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