MSP430 clock setup

Without the complete context (what sample code) I can only guess.
But I can say that it is stupid code anyway. FOR loops won't reliably work for delay. The compile may optimize them away completely as tehy do not influene memory and jsu twaste time (and the compiler doesn't know that wasting time is the intention).
A delay_cycles() instruction is better suited, or the use of a timer. (e.g. counting timer overflows when the timer is clocked by ACLK).

However, the likely reason for the 'magic' numbers is the FLL module (so the code was for 4x or 5x/6x family). The FLL adjusts teh DCO onse modulation step up or down at every reference tick. Since there are 32 modulation steps and 32 DCO steps (of which one is the start point and one is invalid, indicating a wrong RSEL setting), this leaves 30*32 reference clock cycles to be sure that the DCO has settled. I don't knwo why 28 are used. Also, one could start the DCO in the middle and have a maximum of 15*32 ACLK cycles (assuming that the middle DCo setting is still safe for the current operating voltage).

However, when using a MCLK -cycle-based waiting loop, the CPU clock is slower at the beginning and speeds up. (maybe this is why 28 and not 20 is used, but I think you could go even lower). It requires some math to calculate the minimum number of clock cycles to have the FLL settle in worst-case situation (starting fast already and needing all the way up to the highest setting)

I strongly suggest using a timer, counting 15 overflows.