SAR & Sigma Delta ADCs

Two main differences: SAR have much higher sampling rate, Sigma-Delta have way better resolution.

SAR ADCs do each conversion independently of previous ones. Between two samples, you can stop the ADC, reducing power consumption.
Originally, the were a comparator, a DAC and a buffer capacitor. Input value was sampled into the capacitor, then the connection to the singal was sewered and the SAR was comparing the sampled voltage to the DAC output, starting by setting the MSB, keeping the bit in the DAC set if the DAC output was less than the captured voltage, clearign it when the DAC output was higher. (SAR = successive approximation register).
The SAR in the MSP uses switched capacitors charge distribution method to get the bit values, rather than a DAC, but the basic principle is the same.

Slope ADCs use a comparator and a timer. They count the time it takes to charge an internal capacitor from 0V with a constant current until its voltage reaches the input voltage. Again, each sample is independent of the previous. The slope is simpler and cheaper than a SAR, but its converison time varies (conversion takes longer for higher voltages)

Tracking ADCs are sort of slope ADCs, but they start with the last onversion result, charging or discharging the comparison capacitor and adding/subtracting the time it takes. If the sampled voltage doesn't differe much between two conversions, they are much faster than a slope and still cheaper than an SAR.

Flash ADCs use a resistor ladder and individual comparators on each resistor and a priority encoder. They give almost instant onversion results but are very expensive. The linear ones require twice the number of comparators for one bit more resolution. Newer approaches use R/2R resistor ladders where less comparators are required.

Delta-Sigma ADCs (It's not Sigma Delta, even if Ti calls their ADCs "SDxx") use a completely different approach. Here, the input signal is integrated over time and each clock pulse, one bit is emitted showing whether the integrated voltage exceeds the reference. This output bit also controls subtraction of the reference voltage form the input signal (so the delta between input signal and the reference is done first, hence delta-sigma). As a result, the DS-ADC outputs a stream of 0 or 1 bits, one per clock pulse. The relation of 0 and 1 bits for an infinite number of bits is an exact representation of the relation of input signal and reference. Now you don't have infinite time (and don't need infinite resolution), so the bitstream is passed into a digital filter which takes a number of bits and presents a result. The numbe rof bits required is defined in the oversampling ratio (OSR). However, for a converison result, not only OSR new bits ar erequired but also a nubmer fo previous bits. So you cannot stop the ADC if you doN#t want to take a sample. If you don't take continuous samples, you have to drop (in case of the SD16/SD24) the first three conversion results. Teh digital filter gives reliable results only form the 4th subsequent conversion on. As a result, teh Delta-Sigma converters are slow but rather precise while still being relatively cheap to implement.
But don't think that on a 24 bit Delta-sigma you'll get 24 significant bits. That's not the case. If e.g. your MSB is set (the input signal is > 0.5*Vref), teh LSBs are meaningless. Depending on noise and other influences, only the upper bits are significant (on the SD16, you have 10 to 14 significant bits). However, significancedoesn't start with the MSB but with the highest bit that is actually set. So on smaller signals, the lower bits are significant. THis gives you a high dynamic range without sacrificing the resolution on small signals.