MSP430F5438A XT1 Clock Input Duty Cycle Range in Bypass Mode

Darren Beckwith said:

The datasheet says 30% to 70% but it seems like this applies when a crystal is used.

That's the resulting duty cycle of ACLK (should be same for SMCLK or MCLK too) when XT1 runs in LF mode form a 32768Hz crystal.
If you feed a digital square wave to XT1 in bypass mode, the DC of ACLK (SMCLK, MCLK) is the same as the DC of your signal.

However, a 1MHz signal with 10% DC is technically the same as a 5MHz signal with 50% DC and 4 waitstates (missing lcock cycles). And the CPU requires same supply voltage as for 5MHz then.
The limit is that for 20MHz signal, the duty cycle must be in the range of 40..60% (which is the same as for 25MHz 50%)  while on 25MHz, exactly 50% are required.

Jens-Michael,

I don't fully understand your reply. 

Jens-Michael Gross said:

If you feed a digital square wave to XT1 in bypass mode, the DC of ACLK (SMCLK, MCLK) is the same as the DC of your signal.

I realize the the input DC is reflected on the all the clocks of the system.  My problem is we are using a NXP PCF8563 RTC to supply a 32.768kHz digital square wave to the MSP430.  The output DC of the RTC is not guaranteed to be 50% in fact our measurements show it to be 43%.  What I want to know is if the MSP430 will continue to run over temperature with a 32.768kHz digital clock with this duty cycle.

Cheers,
Darren

Darren,

If I'm reading this correctly I could rephrase your question this way. Are the Duty cycle LF mode min and max valid for XT1BYPASS = 1?

The min and max duty cycle on the output of the PCF8563 are not specified.  The DS32KHZ specifies 45% to 65%.

When you feed a TTL clock signal with 43% DC into XTIN in bypass mode, then the resulting ACLK and SMCLK will have 43% DC too.

But the duty cycle has nothing to do with resulting frequency. The number of rising (or falling) edges per second is the same, no matter what the duty cycle is.

Darren Beckwith said:

the the input DC is reflected on the all the clocks of the system

All that are derived from it. Yes. And only if 1:1 taken from the input. if you have a 2:1 divider (or more), then the DC auto-corrects to 50% (the falling edge of the divided frequency comes with the second rising edge of the clock source, so the DC is only affected by clock jitter - different time between two same clock edges - but not by the time between rising and falling clock edges)

In other words: when the clock signal has 32768Hz, it will count 32768 clock pulses per second, no matter what the duty cycle is.

The limiting factor is that a signal with a DC other than 50% is actually a composition of two frequencies, one higher and one lower, whose half clock cycles sum up to a signal with a DC that reflects their percentage on the resulting averaged frequency. And the higher one of these two frequencies must be considered when calculating required supply voltage or maximum frequency limits.

Temperature drift, however, may appear even with a DC of perfect 50%. The two are totally independent. The frequency is influenced by load capacitance, crystal resonance and temperature (and also affected by overvoltage), while the DC is caused/influenced by mechanical asymmetries in the crystal, matching differences on the two load capacitors and unbalanced thresholds in the oscillator circuit.

Tuning the balance of the two load capacitances will adjust the DC. However, changing the total load capacitance will affect the frequency.

Jason Work said:

If I'm reading this correctly I could rephrase your question this way. Is Duty cycle LF mode valid for XT1BYPASS = 1?

Jason,

Not really.  I want to know what minimum and maximum digital square wave DC will cause the MSP430 to not operate correctly.  Here is the clock circuit from our design.