MSP430G2553 help for USCI Interface.

Georgi Rashkov said:

UCA0CTL0 |= UCCKPH + UCMSB + UCMST; //Clock phase,MSB first,Master mode

You need to set UCSYNC here to get SPI mode.

Georgi Rashkov said:

IE2 = UCA0TXIE;

You're enabling the Tx interrupt, but I don't see an ISR. If you ever enable interrupts, your program will crash.

thanks for the help but anyway i have no success with the program! :( there is no error in C code but on the DAC's out doesn't appear anything. This is the full program code:

#include <msp430g2553.h>

void main(void)
{
volatile unsigned int i;

BCSCTL1 = CALBC1_8MHZ; // Set range
DCOCTL = CALDCO_8MHZ; // Set DCO step + modulation */

WDTCTL = WDTPW + WDTHOLD + WDTNMI + WDTNMIES; // WDT off
P1OUT &= ~BIT0; // clear BIT0
P1DIR = BIT0 + BIT4 ; // P1.0 i P1.4 output, else input
P1OUT = BIT0; // P1.0 pullup to hi
P1SEL = BIT2 + BIT4; // P1.2 ->TX, P1.4 -> SMCLK
P1SEL2 = BIT2;

UCA0CTL0 |= UCCKPH + UCMSB + UCMST + UCSYNC + UCMODE_0; //Clock phase,MSB first,Master mode
UCA0CTL1 |= UCSSEL_2; // SMCLK
UCA0CTL1 &= ~UCSWRST; //USCI reset released for operation.
UCA0BR0 = 0; //Bit clock prescaler
UCA0BR1 = 0; //(UCA0BR0 + UCA0BR1 × 256)

IE2 = UCA0TXIE;
__bis_SR_register(CPUOFF + GIE);
}
#pragma vector=USCIAB0TX_VECTOR
__interrupt void USCI0TX_ISR(void)
{
int chA=0xFF; //value chanel A
while (1) //loop
{
P1OUT &= ~BIT0; // enable CS (to Low)
UCA0TXBUF =0x09; // Send command
while (!(IFG2 & UCA0TXIFG)); // wait for TX buffer ready
__delay_cycles(10);

UCA0TXBUF = chA; // Send wiper level
while (!(IFG2 & UCA0TXIFG)); // wait for TX buffer ready
while (UCA0STAT & UCBUSY); // wait for the tx to complete
P1OUT |= BIT0; // disable Slave (CS to High)
__delay_cycles(10);
}
}

REGARDS 

G.Gashev said:

UCA0BR0 = 0; //Bit clock prescaler
UCA0BR1 = 0; //(UCA0BR0 + UCA0BR1 × 256)

Hmmm, you divide the clock by zero. What baudrate do you expect? Infinite? If you want to use maximum clock, use UCA0BR0=1;
Also, the prescalers must be set before clearing SWRST.

G.Gashev said:

P1SEL = BIT2 + BIT4; // P1.2 ->TX, P1.4 -> SMCLK
P1SEL2 = BIT2;

Well, SPI requires at least two signals from teh USCI, (MOSI or MISO, usually both) and CLK. However, you only set P1.2 (UCA0SIMO) into USCI mode. P1.4(UCA0CLK) is put into SMCLK output mode. This way, the slave will get a continuous clock signal and 'reads' data all the time from the inactive SOMI pin. And only if by coincidence the USCI sends something, the slave will receive it - not necessarily byte-aligned - and then reads dummy data again.

You need to set BIT4 in P1SEL2 too, so the slave only gets a clock signal when the USCI is sending something.

G.Gashev said:

there is no error in C code

Well, the code is syntactically correct, but not functionally. But the compiler of course can only check for formal (syntax) errors.