MSP-FET430UIF "Error initializing emulator: Could not initialize device interface" error in CCS 5.2.1

1) The error seems to indicate that the software cannot establish a connection to the FET.
In the past, this has been often tracked down to 3rd party software that was hijacking the virtual COM port as soon as it appears, such as mobile devices (smartphone) comm software or even mouse drivers.
Sometimes this software is so badly written that it doesn't notice that the FET is no smartphone/mouse.

2) past reports indicate that the driver isntallaiton may be shakey under Win8. 64 bit will surely increase the problem. Especially since the drivers areN't M$ signed for WIn8.

3) Well, once you got it working, you know that the wirings are correct. X-ray inspection would require a workign sample for comparison :)

4) If you're taling about the pull-down cap on RST, well, it is required for non-ideal power supplies (non-instantaneous voltage). The slower voltage rises, the larger it must be. Up to a certain point, it is not necessary at all. I use 100nF, but I don't use SBW (serial JTAG), where 2.2nF are the max.

5) I never had the Elprotronic software crashing. It too indicates a driver or application conflict.

6) If you don't use analog functions, you may connect AVCC/DVCC and AVSS/DVSS or even leave the analog supplie sopen (they are internally connected through clamp diodes).
If you use analog functions, you should
- connect AVCC to DVCC through a 10Ohm or 33Ohm resistor (smaller, if you use a DAC and need analog output current), and a 100nF ceramic/10µF Tantalum combo. This decouples the analog voltage from any digital ripples. (the clamp diode threshodl voltage is much higher than any ripples, the diode doesn't conduct at all in this case).
- route AVSS and DVSS separately to the supply. This way, any supply return current from digital circutry (on DVSS GND) won't induct voltage ripples on the analog GND. Use the analog GND for any GND reference of external circuitry too. Here again, teh clamp diodes in teh MSp won't allow the two GNDs to drift too far apart but won't conduct on small rupples.

This keeps your analog voltage references clean.

Regarding 'unused' pins: the mainconcern with unused pins is the high input impedance of CMOS inputs that allows static voltage levels to build up on isolated pins and their stray capacity. The may even catch radio waves and oscillate. Aslo, if the input voltage is near the transition voltage of the input, internal cross-currents will flow (two opposite transistors are conducting in the input circuitry), causing increased power consumption. Therefore all pins wiht digital input capability should be turned into low output mode if not externally connected.

Jens, thank you very much for your prompt response!

I have a few follow-up questions:

1) Given that CCS found the FET and updated its firmware, doesn't that suggest that CCS can find it and there's no driver conflict? How would I determine if there's an interfering driver? Is there a way to make sure the FET was updated properly and there's not something wrong with it?

2) Do you think I can use the FET in Win8 by running CCS in compatibility mode? or would that not have an effect on how the FET VCP is run? Would it be better to run on Win7 instead (I do have access to a Win7 32 machine)?

3) Thanks.. for now, I'm going to assume it's ok since I don't have access to an X-ray machine, lol

4) Thanks!

5) hmm..

6) ok
     - Could you clarify the arrangement of the resistor and capacitors between Avcc and Dvcc? I read it as the resistor and capacitors are in parallel with each other, and the group is in series between Avcc and Dvcc. Like: Avcc-----(ceramic // resistor // Tantalum)-----Dvcc
     - So, the Avss and Dvss ground traces are separate as they are routed back to the regulator ground pin, at which point they both connect to the same pin. Did I understand that correctly? Do I also understand that (if I was making a PCB) the analog ground would also be the ground pour around the rest of the board? Would I need capacitors between the analog and digital ground traces, or the analog pour and digital traces? I've never done this before, can you point me to a good resource for this info?
     - So, once I setup the ports correctly I won't have any "unused" pins, I won't receive the warnings in CCS, and won't have to worry about how to connect them?

Up till now I feel like I've been going in circles, so I really appreciate your comments! Thank you!

Victor Skulavik II

Victor Skulavik II said:

1) Given that CCS found the FET and updated its firmware, doesn't that suggest that CCS can find it and there's no driver conflict?

Yes and no. Maybe jsut after the update, the changed response of the FET causes the offending interfering software to hijack it. :)
Maybe the update failed.

What you can try: look into device manager for the MSPs COM port, then try to open this COM port with HyperTerm or another terminal program. You should get an error if the port is in use.

I'm definitely no FET expert. I don't even use CCS or IAR, and the Elprotronic software never tried to update the firmware. So I cannot tell you what could have gone wrong or how to detect whether it is right. I'm sure there is an identification sequence of some sort, but I really don't know. Well, teh green LED should light up when you plug the FET into USB. That's all I can tell.

But there are many other threads about FET problems. Maybe you'll find some info there.

2) IMHO (and I'm no Win8 user and cannot understand how someone can use it in a productivity environment at all, at least before the second service pack) the problem are the drives (and how Win8 tortures them) and not CCS. CCS is only using a DLL (MSP430.dll) which in turn only does a normal serial communication through a COM port.

3) well, it was only partly a joke. The only way to ensure valid hardware is to compare it with a known working version with sufficient resolution. And comparing X-Ray images is indeed something that is often used. Or, in simple rcases, comparing digital cam images. Depends on application.

5) I should add that we use XP on our development and production PCs. No experiments. Especially nto with a new and widely untested Windows version.

Victor Skulavik II said:

I read it as the resistor and capacitors are in parallel with each other

No, the resistor is between DVCC and AVCC and the caps are between AVCC and AVSS. A cap parallel to the resistor would short the resistor for transientes. Quite the opposite of what is required.

No caps between analog and digital ground. Those caps would just forward the voltage ripple fo the digital gnd to the analog gnd. It would best to keep the two as far away as possible (at least don't put a single AGND trace on a DGND plane with only a small gap between). One can go as far as routing AGND on the top layer when the bottom layer is a GND plane, and include a gap on the gnd plane where the AGND trace is - to reduce stray capacitance. But in the very most cases this is pure overkill.

Whether you use AGND or DGND as GND plane (if usign a GND plane at all) depends on applciation. Usually, it's better to have digital GND on the GND plane (or pour) as it carries the higher currents. Stretching it across a plane reduces crosstalk a bit. However, don't expect the current s in a GND plane to be evently distributed. They tend to flow where an opposite current flows on the other layer. Well, we noticed this effect when we modulated 30A for a laser. A GDN pour and a GND plane are also acting a bit different. Again, things like this depend on application and required precision and resolution.

Victor Skulavik II said:

can you point me to a good resource for this info?

Sorry, Most of my knowledge is based on own experience or things that I read once in an electronics magazine (not the hobbyist stuff) over the last 25 years. I don't have any (online or offline) resources I could point you to.

I haven't worked with the ULP advisor as I don't use CCS. So I don't know what warnings it will emit when. However, the ULP advisor warnings are no showstoppers for a workign applicaiton. They are mainly addressed towards low power consumption (avoiding unnecessary power draws) and do not influence the application. In some cases, (especially regarding unused interrupt vectors) they may even obfuscate a software bug, as the analysis is too generic to separate real problems from potential problems. But it's a new software and improvements are to be expected in future :)

Victor Skulavik II said:

Up till now I feel like I've been going in circles

I know this feeling. I have it almost always when I start a new poject. Don't try doing all at once. Separate the problem into smaller units and solve them independently. this way the 'circles' are kept small and you can bend them into lines one after another. :)