MSP430F5510, multibyte SPI transfer using DMA

Maxim Danilov said:

2. trigger transmission by toggling UCTXIFG bit

I'm not sure whether this works. My onw code triggers the transfer by writing the first dummy byte manually.

Why do you enable DMA interrupt for both, TX and RX channel? RX is sufficient.

Is the USCI set up properly? Especially you may not configure the USCI to trigger an interrupt itself, or the DMA doesn't get triggered.

I'm not familiar with the API you use. What are DMA_TRIGGER_HIGH and DMA_TRIGGER_RISINGEDGE  and why do you set DMA_TRIGGER_HIGH on DMA_init, bti DMA_TRIGGER_RISINGEDGE on DMA_setScrAddress?

Note that you may only use edge-triggered DMA except for external DMA trigger which may be level triggered too.

Maxim Danilov said:

while(flash_dma_active); // flag is reset in ISR

I hope that flash_dma_active is a volatile variable?

Jens-Michael, thanks for your reply!

Jens-Michael Gross said:

2. trigger transmission by toggling UCTXIFG bit

I'm not sure whether this works. My onw code triggers the transfer by writing the first dummy byte manually.

[/quote]

That trick works!

Jens-Michael Gross said:

Is the USCI set up properly? Especially you may not configure the USCI to trigger an interrupt itself, or the DMA doesn't get triggered.

Thanks, that was the case, USCI interrupts were enabled.

Jens-Michael Gross said:

I'm not familiar with the API you use. What are DMA_TRIGGER_HIGH and DMA_TRIGGER_RISINGEDGE  and why do you set DMA_TRIGGER_HIGH on DMA_init, bti DMA_TRIGGER_RISINGEDGE on DMA_setScrAddress?

That was a typo.

Jens-Michael Gross said:

while(flash_dma_active); // flag is reset in ISR

I hope that flash_dma_active is a volatile variable?

[/quote]

Yes, it's volatile.

Final version of code (works properly) looks like this:

#define FLASH_DMA_CHANNEL_RX            DMA_CHANNEL_2
#define FLASH_DMA_CHANNEL_TX            DMA_CHANNEL_1
#define FLASH_DMA_SOURCE_TX                DMA_TRIGGERSOURCE_23
#define FLASH_DMA_SOURCE_RX                DMA_TRIGGERSOURCE_22

    uint8_t dummy_byte = FLASH_ANY;
    // TX
    DMA_init(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_TX, DMA_TRANSFER_SINGLE, length, FLASH_DMA_SOURCE_TX, DMA_SIZE_SRCBYTE_DSTBYTE, DMA_TRIGGER_HIGH);

    DMA_setSrcAddress(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_TX, (uint32_t)&dummy_byte, DMA_DIRECTION_UNCHANGED);

    DMA_setDstAddress(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_TX, SPI_getTransmitBufferAddressForDMA(__MSP430_BASEADDRESS_USCI_B1__), DMA_DIRECTION_UNCHANGED);
    // no interrupt needed for TX

    // RX
    DMA_init(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_RX, DMA_TRANSFER_SINGLE, length, FLASH_DMA_SOURCE_RX, DMA_SIZE_SRCBYTE_DSTBYTE, DMA_TRIGGER_HIGH);
    DMA_setSrcAddress(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_RX, SPI_getReceiveBufferAddressForDMA(__MSP430_BASEADDRESS_USCI_B1__), DMA_DIRECTION_UNCHANGED);
    DMA_setDstAddress(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_RX, (uint32_t)&(dst[0]), DMA_DIRECTION_INCREMENT);

    DMA_enableInterrupt(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_RX);

    flash_dma_active = true; // volatile one, used to indicate the end of transfer

    DMA_enableTransfers(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_RX);
    DMA_enableTransfers(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_TX);

    UCB1IFG &= ~UCTXIFG;
    UCB1IFG |=  UCTXIFG;

    while(flash_dma_active); // is reset in DMA ISR

    DMA_clearInterrupt(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_RX);
    DMA_disableInterrupt(__MSP430_BASEADDRESS_DMAX_3__, FLASH_DMA_CHANNEL_RX);