cc430F5xx USCI SPI Interrupt Vector

Hello,

I try to understand USCI spi for 5xx series. I wrote a code model TI's example codes. This code's aim is only sending always 0x55 from its MOSI pin. There is no data coming to RX pin. But when i debugged the code there is a problem which i couldn't understand.  I realized, after send 0x55 from MOSI (putting 0x55 to UCA0TXBUF register),    UCRXIFG is set and program branchs to interrupt vector with UCA0IV=2. And then every time after putting some value UCATXBUF register, UCRXIF is set and branching to int. vector. How can it can be, because there is no data at MISO pin so there is no receiving data.

The code is below,

#include "msp430.h"

unsigned char MST_Data;

void main(void)
{
  WDTCTL = WDTPW+WDTHOLD;                   // Stop watchdog timer

  PMAPPWD = 0x02D52;                        // Get write-access to port mapping regs  
  P1MAP5 = PM_UCA0SIMO;                     // Map UCA0SIMO output to P2.0
  P1MAP6 = PM_UCA0SOMI;                     // Map UCA0SOMI output to P2.2
  P1MAP7 = PM_UCA0CLK;                      // Map UCA0CLK output to P2.4
  PMAPPWD = 0;                              // Lock port mapping registers  
   

  P1DIR |= BIT5 + BIT6 + BIT7;                       // ACLK, MCLK, SMCLK set out to pins
  P1SEL |= BIT5 + BIT6 + BIT7;                       // P2.0,2,4 for debugging purposes.

  UCA0CTL1 |= UCSWRST;                              // **Put state machine in reset**
  UCA0CTL0 |= UCMST+UCSYNC+UCCKPL+UCMSB;    // 3-pin, 8-bit SPI master
                                                                                     // Clock polarity high, MSB
  UCA0CTL1 |= UCSSEL_2;                          // SMCLK
  UCA0BR0 = 0x02;                                      // /2
  UCA0BR1 = 0;                                           //
  UCA0MCTL = 0;                                      // No modulation
  UCA0CTL1 &= ~UCSWRST;                     // **Initialize USCI state machine**
  UCA0IE |= UCRXIE;                         // Enable USCI_A0 RX interrupt

  __delay_cycles(100);                      // Wait for slave to initialize

  MST_Data = 0x01;                          // Initialize data values


  while (!(UCA0IFG&UCTXIFG));                             // USCI_A0 TX buffer ready?
  UCA0TXBUF = 0x55;__delay_cycles(100);               // Transmit first character

  __bis_SR_register(LPM0_bits + GIE);                   // CPU off, enable interrupts
}

#pragma vector=USCI_A0_VECTOR
__interrupt void USCI_A0_ISR(void)
{
  switch(__even_in_range(UCA0IV,4))
  {
    case 0: break;                                        // Vector 0 - no interrupt
    case 2:                                                   // Vector 2 - RXIFG
      while (!(UCA0IFG&UCTXIFG));           // USCI_A0 TX buffer ready?
      UCA0TXBUF = MST_Data;                 // Send next value

      __delay_cycles(40);                             // Add time between transmissions to
                                                                  // make sure slave can process information
      break;
    case 4: break;                                       // Vector 4 - TXIFG
    default: break;
  }
}