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Huge temperature drift on SD24_B ?

Manuel Lopez
Prodigy 20 points
Other Parts Discussed in Thread: MSP430F6733

I'm currently working on a project that relies on a MSP430F6733 MCU and its sigma-delta ADC, the SD24_B module.

We had some problems which we found out are being caused by a huge temperature drift on the readings from SD24_B.

I was wondering if anyone has had a similar problem.

Here is some data on our setup:

->GAIN is 1 

->sd24 clock is 2,27Mhz (25Mhz / 11)

->2 OSR settings tested with similar results (32,128)

->input is a known voltage from a precision source (0.5V)

->internal VREF, coupled with a capacitor as suggested in the datasheet.

->VREF pin monitored for changes

During our testing, the value obtained from converter 0 decreased significantly when applying heat to the chip ( with a fancy industrial 'hair dryer' ).

We monitored this value from the debugger.

The chip was never too hot, only warm to the touch. (Sadly I don't have exact temperature readings)

The changes were proportional to applied heat (It didn't 'break' or stop working.)

Removing heat made the values slowly go back to the starting values.

Only very small changes in VREF detected. We have discarded that the cause is a variation in VREF with temperature. We monitored this value through an external multimeter.

Sadly I don't have numbers right now, but I hope this information is enough for you.

Any ideas on this?

Thanks for your time.

  • 0
    Guru 227245 points

    Manuel Lopez said:
    We monitored this value from the debugger.

    Does it mean you stop the MSP after each conversion to read the result through JTAG?
    The Delta-Sigma converters require a constant operation for reliable results. Entering a debugge rbreakpoint usually stops the clocks, and if you run the SD24 from SMCLK rathe rthan ints internal MODOSC, this means the SD24 stops samplign the input. This in turn renders the next three conversion results useless.

    Where do you get the 25MHz from? Does frequency drift with temperature? 2.27MHz is close to the maximum of 2.3MHz (beyond, the SD24 will likely start drifting). It's possible that with raising clock speed, the converison loop is affected by low-pass effects.
    If you can bear the slower conversion time, you should try with a slower SD24 clock (e.g. 25MHz/12 or /13).

    Just an idea.

  • 0 in reply to Jens-Michael Gross
    Prodigy 20 points

    Jens-Michael Gross said:

     2.27MHz is close to the maximum of 2.3MHz 

    Bingo! Actually we fixed this problem last week after a lot of headaches. By elimination we found out the only difference left between our code and  a TI example that worked was the clock frequency. We ended up using a slower clock frequency (around 1.25Mhz) with much better results.
    Thanks for the help anyways!

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