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MSP430F1611 USART I2C glitch workaround

Other Parts Discussed in Thread: MSP430F1611, MSP430F2618

Before I conclude what I've discovered, I want to share here.

Situation:

MSP430F1611 I2C Master Write every 20 seconds. (No interrupt used, only by polling IFGs)

In between Master Write, 1611 becomes Slave as USART I2C automatically clears MST bit. -> Normal

While in LPM mode for 20 seconds as slave, if a glitch is induced to I2C Bus, 1611 sometime recognize the glitch as START Condition. -> Normal

Then 1611 sets I2CBUSY, I2CBB as 1611 is in Slave mode now -> Normal

After 20 Seconds passed, 1611 Master Write, but ALIFG is set as I2CBB is not cleared. -> Normal

So No data cannot be sent. -> Normal

So i tried to clear I2CBB by clearing I2CEN in the beginning every time 1611 starts the transfer.

Well, THIS DID NOT WORK. -> Abnormal

Somehow I2C hardware module states machine got corrupted?

But I discovered following Master Write works fine.

Then i wonder, maybe clearing I2CEN one time is not enough when I2C state machine got corrupted.

So i add code to re-set I2CEN 10 times before I start the transfer. (10 times .. no solid reason just wanted to do many)

I do this following for every transfer.

void i2c_masterInit(uint8_t selctClockSource, uint8_t preScalerValue, uint8_t clockHighValue, uint8_t clockLowValue)
{


volatile uint8_t i;

// No repeat mode implementation I2CRM = 0
// DO NOT Init when previous transfer is being processed!!!
// checking the i2c status before init is important as we'll call init every time we transfer
U0CTL |= I2C + SYNC; // Recommended init procedure

for( i = 0 ; i < 10 ; i++)
{

U0CTL &= ~I2CEN;
U0CTL |= I2CEN;

}

U0CTL &= ~I2CEN; // Disable I2C
I2CTCTL = selctClockSource; // SMCLK mostly
I2CPSC = preScalerValue; //I2CPSC should be <=4 or error might occur
I2CSCLH = clockHighValue; // High period of SCL (I2CSCLH+2) x (I2CPSC+ 1)
I2CSCLL = clockLowValue; // Low period of SCL (I2CSCLL+2) x (I2CPSC + 1)
I2CNDAT = 0; // initialize data cnt;
U0CTL |= I2CEN; // Enable I2C
U0CTL |= MST; // set to Master mode to I2C register

}

May this workaround is already in Errata sheet but i did not fully understand, but hope this can help other people.

If any TI employee can confirm this i'd appreciate.

Or i think i might have to change IC to MSP430F2618 or similar with USCI I2C.

And if I made wrong assumption, please correct me.

thank you 

  • Ho-Jun Song said:
    So i tried to clear I2CBB by clearing I2CEN in the beginning every time 1611 starts the transfer.

    I2CEN is not resetting the module, it is jsut putting it into inactive or active state.

    To really reset the module, you'll need to clear and then set the I2C and SYNC bits, so teh USART is switched to SPI or UART mode temporarily. This will ensure thet I2C module is re-initialized.
    This is a bit different than the SWRST operation of the I2CEN bit in SPI or UART mode (and likely that's why it isn't called SWRST in I2C mode)

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