• State
  • Locked Locked
  • Replies 2 replies
  • Subscribers 79 subscribers
  • Views 2926 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

SPI frame format

John Flanno
Intellectual 635 points


I have 16 bits of data . I have to send it to slave device . First i have to select slave signal and pull clock line low to start transmission . After that depending upon mode bit will transferred ouit and received on master . MY doubt is SPI send only 8 bit data after sending 8 bit data do we need to pull SSEL line high and then low or we can send any number of data continously?

In slave mode, if the
SS line is not deasserted between the successive transmissions then the content of the
SPI Data Register is not transmitted, instead the last received byte is transmitted. If the
SS line is
deasserted for at least minimum idle time ( half SCK cycle)  between successive transmissions then the
content of the SPI Data Register is transmitted.
In master mode, with slave select output enabled the
SS line is always deasserted and reasserted between
successive transfers for at least minimum idle time.

Bolded part was found in SPI motorola spec . So if i have to send 16 bits of data i have to deassert  (pull SS to high then to low?) then transfer another 8 bits?

  • 0
    Guru 46710 points

    John Flanno said:
    motorola spec

    Unless you are building some kind of universal SPI i/o controller/debugger/whatever which shall support all the wide variety of various SPI chips, you can skip reading motorola SPI book. Instead read manuals of SPI chips you are going to use. Please realize that there's no such thing as SPI standard, implementations vary.

    John Flanno said:
    So if i have to send 16 bits of data i have to deassert  (pull SS to high then to low?) then transfer another 8 bits?

    Usually no - for SPI slaves having more than 16 bits of "memory"/register. For example you can read whole contents of SPI flash in one pass, without touching SS after assert. When transfer done - only then you raise SS.

  • 0
    Guru 227245 points

    The bold part sdescribes a specific implementation of SPI for a specific slave.

    Thsi slave will only send its transmit register content right after being selected. Form then on, it will echo incoming data unless you deselect and reselect it. However, this is a very specific implementation.

    Usually, assering chip select synchronizes the slave with the bus. Depending on slave, it can mean start of a new high-level protocol frame, or just synchronize the clock to a byte border. On some slaves, not even this (those slaves simply ignore the bus if CS is high and clock bits in whn CS is low).

    Besides this, SPi is just an endless stream of bits, which are interpreted as bytes, words, dwords or whatever.
    Teh USI module in some MSPs supports sending one to 16 bits at a  time, teh USCI supports only a granularity of 8 bits.

    Whether the slave interprets this data as a byte, a word, a 24 bit value or even a complex array of data elements of different size, depends on the slave.

**Attention** This is a public forum