MSP430 sampling frequency

Hello,

I dont know if my answer is 100%true, but I did use ADC with MSP430F5437A and my datasheet stated something similar. Maximum ADC clokc about 5,4 MHz. I did understand that it is simply not possible to use a higher clock speed for the ADC, so I think in your case it will be the same, you simply cannot use a higher clock rate.

If you dont give your ADC an external clock within the range it will be variable, so you simply do not know the exact timing, which might be ok for some applications for some not, so that is yours to decide.

Hope that helps a bit.

Hi,

FSSer said:

The Date sheet is described as follows

(slas722e 34page) ADC10 incpu clock frequency
0.45MHz ～ 6.3MHz

as you've already taken from the data sheet, the maximum ADC10 input clock frequency is 6.3 MHz. You have to adjust your clock frequency setting in order that it is within specified and acceptable limits.

FSSer said:

But, I want to set 16MHz to ADC10CLK.

You will get less accurate or even useless results at higher frequencies than 6.3 MHz. Limits and parameters are given that the error in a conversion is less than ±0.5 LSB.
I wonder why maximum limits are given in the data sheet if nobody would keep to it? Have you already made some test measurements at defined reference voltages with 16 MHz input clock frequency? Then you can determine whether you get right results at all. I bet not.

Best regards,
Christian

Christian Steffen said:

You will get less accurate or even useless results at higher frequencies than 6.3 MHz.

At 16MHz, I'd say 'useless'. Experiments have shown that even 8MHz are pushing the results far beyond teh specified performance.
ADC10 uses charge distribution method. To let the internal capacitors redistribute their charge, a certain minimum time is required. If the clock is too fast, charge cannot flow as required and results are unpredictable. If the clock is too low, leakage currents and other effects will also negatively affect the result beyond the specified performance.

Thank you everyone .

I was very helpful.

I'll try to consider using in 0.45MHz ～ 6.3MHz.

 

 

FSSer said:

ADC10CLK = 16MHz

Time to convert(13cycle) from sampling(4cycle)
(4 + 13) x 62.5nsec = 1062.5nsec

This is correct?

Yes, the calculation itself is correct. But you won't get a reliable result with these settings. Teh internal structure of the ADC10, which uses teh charge-distribution method for teh conversion, requires some minimum and maximum time per conversion step. if you clock it too slow, leakage currents will cause a wrong result. If you clock it too fast, the charges don't have enough time to flow insicde the circuitry, giving wrong results too.

It's like with a processor, e.g. a Pentium: you simply cannot just rise the supply voltage and then run it on a higher clock speed. This works fine at first, then the processor won't run stable and finally won't run at  all.