Hello people,
Coul you help me with a question. What´s the function of the C2 and C3 in the diagram attached?
Thank you very much,
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Hello people,
Coul you help me with a question. What´s the function of the C2 and C3 in the diagram attached?
Thank you very much,
It seems that this schematic has been simplyfied beyond sense.
10µF (tantalum) is prett much useless as support capacitor to DVcc. 100nF deblocking/bypass are good to have everywhere where you have digital operations that cause current transients.
Thsi specific combination of 10µF tantalum + 100nF ceramic is used to filter noise from AVcc. For this to work, you'll have to separate AVcc from DVcc by a series resistor (10R-100R). AVcc doesn't draw much current, but the voltage should be stable. So the two capacitors behind the series resistor filter out any ripple on Vcc caused by DVcc.
The same two caps are usually placed on VRef when externally emitted (required on some MSPs, optional on others)
It is recommended too, to route DVss and AVss separately, so currents on DVss don't cause a voltage drop that shifts the analog ground reference. The two signals should be connected at the GND point of the power supply.
For R1, it is suggested on systems where SBW is used, that R1 and a 100nF pulldown capacitor are not directly connected to RST pin but through a 1k series resistor. This prohibits the capacitor to apply a low-pass filter to the SBW signal while still allowing for the power-on pulldown of RTS.
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