Hi all,
My name is Kevin Meyer and I am a student at Boston University. One component of my senior design project involves interfacing an MSP430 with an EEProm, specifically the SST25VF016B. Right all I am trying to do is read the status register of the EE prom. Thus far, I have been unsuccessful in this task. The status reigster is either all zeros or all ones. (it should read 0x1C) If you could offer any insight into my problem it would be greatly appreciated. Below are relevant portions of code and the schematic I am using to connect the device. Most of my code is based on an application note. I am using the USCI_B1 communications module (SPI).
Thank you for your time,
Kevin
#include <msp430f5529.h>
#define SCLK BIT3 //P4.3 Slave Clock
#define SOMI BIT2 //P4.2 Slave out master in
#define SIMO BIT1 //P4.1 Slave in master out
#define CE BIT0 //P4.0 Clock of system
#define READ 0x03 // READ instruction
#define WRITE 0x02 // WRITE instruction
#define WREN 0x06 // WRITE ENABLE instruction
#define RDSR 0x05 // READ STATUS register instruction
#define WRSR 0x01 // WRITE STATUS REGISTER instruction
#define NOPROT 0x00 // disable all write protections
unsigned int i=0;
unsigned char status_register=0x00;
void flash_init_gpio(void)
{
P4SEL |= SOMI + SIMO + SCLK; // P3.3,4 use special function
P4DIR |= CE; //Set P3.0 Gpio as chip enable
P4OUT |= CE;
}
void flash_init_module(void)
{
UCB1CTL1 |= UCSWRST; // **Put state machine in reset**
/*
Bit 7: Clock phase select
Clear UCCKPH...data is changed on first UCLK edge and captured on following
Bit 6: Clock polarity select
Clear UCCKPL...inactive state is low
Bit 5: Direction of recieve and transmt shift register
Set UCMSB...MSB first
Bit 4: Character Length
Clear UC7BIT...8-bit data
Bit 3: Master mode select
Set UCMST...Master mode (msp430 provides clock)
Bit 2-1: 4-pin SPI with CE (UCxSTE active low) (slave enabled when UCxSTE=0)
UCMODEx=00 or set UCMODE_0
Bit 0: Synchronous mode enable
Set UCSYNC Bit...Synchronous mode
*/
UCB1CTL0 &= ~(UCCKPH + UUCKPL + UC7BIT);
UCB1CTL0 |= UCMSB + UCMST + UCMODE_0 + UCSYNC;
UCB1CTL1 |= UCSSEL_2; // SMCLK
UCB1BR0 = 0x02; // /2
UCB1BR1 = 0; //
UCB1CTL1 &= ~UCSWRST; // **Initialize USCI state machine**
UCB1IE |= UCRXIE; // Enable USCI_A0 RX interrupt
}
/*Basic Function: Chip enable/diable, basic write, basic read */
void chip_enable(void)//enable chip through SS line
{
P3OUT |= CE;
P3OUT &= ~CE;
}
void chip_disable(void)//disable chip through
{
P3OUT &= ~CE;
P3OUT |= CE;
}
void write(unsigned char byte)
{
while (!(UCB1IFG & UCTXIFG)); // USCI_A0 TX buffer ready?
UCB1TXBUF = byte; // Transmit message
while (!(UCB1IFG & UCRXIFG)); // wait until something receives. This also means that sending is completed
UCB1IFG &= ~ UCRXIFG; //clear flag
}
unsigned char read(void) //read a 8bit character
{
write(0xFF);//clear buffer
return UCB1RXBUF;
}
/* write enable, write protect, and Status Register Functions */
void write_enable(void)//enable writng
{
chip_enable();
write(WREN);
chip_diable();
}
void disable_writeprotect(void)
{
write_enable();
write_status_register(0x00);//write no protection
}
void write_status_register(unsigned char status)//write to status register
{
chip_enable();
write(WRSR);
write(status);
chip_disable();
_delay_cycles(10000);//should be 5 ms ...try using timers
is_busy();
}
unsigned char read_status_register(void)
{
unsigned char status_reg;
chip_enable();
write(0x05);
status_reg=read();
chip_disable();
return status_reg;
}
void is_busy(void)//polls to see if status register bit is still busy
{
while(read_status_register() & 0x01);//stuck in this function while the flash is busy
}
void main(void)
{
WDTCTL = WDTPW+WDTHOLD; // Stop watchdog timer
flash_init_gpio();
flash_init_module();
_delay_cycles(100000);//wait for flash to power up
read_status_register();//read status register
__bis_SR_register(LPM4_bits + GIE); // Enter LPM4, enable interrupts
}
