CC430 RTC issue

P.S. I forgot to say that MCU VCC = 2.88 Volt

and i test the Clock frequency in room temperature.

My RTC Initialize:

RTCCTL01 = RTCTEVIE + RTCMODE + RTCSSEL_0 +RTCTEV__HOUR 
RTCPS0CTL = RT0PSDIV_2; 
RTCPS1CTL = RT1SSEL_2 + RT1PSDIV_3;

goodarz kashian said:

also i have added  a 12 pF external capacitor and disabled the internal cap but no use.

One 12pF capacitor? Or two 22pF caps (in addition with 2*2pF pin capacitance and wihtout additional trace capacitance this gives 12pF load then).

However, the drift you observe is 8.3% (5min/hr) or 1.4% (1hr/3d) while the difference in teh crystal spee d(if you can trust your scope) is only 0.4% off.

Now the question is: how do you count the time?

If you set up a timer that gives an interrupt every 32768 ACLK (crystal) ticks, you'd get an interrupt every second and can count it. You shouldn't be more than 0.4% off.

However, your code doesn't perform the proper procedure to set up the crystal. You don't clear the fault bits etc. So you're still running on REFO fallback. See the users guide clock chapter for details.

goodarz kashian said:

UCSCTL3 |= SELA__XT1CLK; // Select XT1 as FLL reference

UCSCTL3 holds the frequency factor, not the reference setting. Since SELA_CT1CLK is 0x00, it doesn't do any harm but is wrong nonetheless.

Hello,

thank you Jens-Michael for your reply,

as you mentioned there are some mistakes with my clock initialization

basically i have corrected the code as below:

[My Clock initialization code]

// Disable all interrupts

__disable_interrupt();

//Hold Watchdog Timer
WDTCTL = WDTPW + WDTHOLD;

//Increase CPU Core Voltage (For Radio + FLL)
SetVCore(3);

// Initialize XT1 Pins
P5SEL |= 0x03;
// Turn ON XT1 + XT1 is in Low Frequency mode
UCSCTL6 &= ~(XT1OFF + XTS);
// Low-frequency mode + Internal Load cap       <-- Internal Capacitor
UCSCTL6 |= (XCAP_3 + XT1DRIVE_3);

// Maintain the reset values
UCSCTL5 = 0x0000;

// ACLK source = XT1CLK + SMCLK source = DCOCLKDIV + MCLK source = DCOCLKDIV
UCSCTL4 |= (SELA__XT1CLK + SELS__DCOCLKDIV + SELM__DCOCLKDIV);

// Maintain the reset values
UCSCTL3 = 0x0000;

// Loop until XT1,XT2 & DCO stabilizes
do
{
// Clear XT2,XT1,DCO fault flags
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG;
}while (SFRIFG1&OFIFG);

// Xtal is now stable, reduce drive strength
UCSCTL6 &= ~(XT1DRIVE_3);


// Configure CPU clock for 12MHz
_BIS_SR(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_5; // Select suitable range
UCSCTL2 = FLLD_1 + 0x16E; // Set DCO Multiplier
_BIC_SR(SCG0); // Enable the FLL control loop

// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 12 MHz / 32,768 Hz = 375000 = MCLK cycles for DCO to settle
__delay_cycles(375000);

// Loop until XT1 & DCO stabilizes, use do-while to insure that
// body is executed at least once
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
SFRIFG1 &= ~OFIFG; // Clear fault flags
}
while ((SFRIFG1 & OFIFG));

i checked my Xtall (MS1V-T1KV) datasheet again and i saw the "load capacitance" for 32KHz is about ~ 7pF

and from the CC430 Family datasheet (SLAU259E,  page 128) the C(eff) ~ (C(Xin) + 2pF) /2

so:

C(eff) ~ (7 pF + 2pF) /2   ---> nearest C(eff) ~ 5.5pF 

[Does my  calculations correct ?]

(with XCAP_1  & XTS = 0) --> C = 5.5 pF

(with XCAP_3  & XTS = 0) -->  C  = 12  pF

[which one should i select ?]

then i check the ACLK frequency with my oscope again

and still the ACLK is look like with the former waveform (with 32.89 KHz)

is there any margin for frequency drift in ACLK (for example 10 Hz drift is ok ??)

and my RTC is still running faster than my computer clock. :( 

Jens-Michael Gross said:

Now the question is: how do you count the time?

I have configured RTC in calender mode and I display the time and date with these formats on LCD    

CLOCK = (HH24 : MM : SS) 

Date = (YY : MM : DD)

in the main of the program i sync the time with my computer (manually) and leave the board running. (i sync the time with max 1 sec drift)

i display the time on LCD in the ISR of my timer1 (with a 32ms interval also a delay for show the time and date on LCD) 

and this is the method for reading the time from RTC:

#define RTC_VALID_READ_MAX_WAIT  12000U

void RTC_GetTime(void)

{
u16_t wait_counter = 0;
 /* Wait for RTCRDY to go high, so read will be valid. */
while (!(RTCCTL01&RTCRDY))
{
wait_counter++;
if (wait_counter > RTC_VALID_READ_MAX_WAIT) break;
}
if (wait_counter<=RTC_VALID_READ_MAX_WAIT)
{
Time.Second=RTCSEC;
Time.Minute=RTCMIN;
Time.Hour=RTCHOUR;
}

}

 --> then I display the "Time.Second & Time.Minute & Time.Hour" on LCD.

i check the board like a table clock and each 1 hour i check the clock with my computer time.

Jens-Michael Gross said:

One 12pF capacitor? Or two 22pF caps (in addition with 2*2pF pin capacitance and wihtout additional trace capacitance this gives 12pF load then).

i use two 12pF capacitor connected to each pin as below:

Any Answers ?

SOS :-)

goodarz kashian said:

C(eff) ~ (7 pF + 2pF) /2   ---> nearest C(eff) ~ 5.5pF
[Does my  calculations correct ?]

No. C_L, as stated in the datasheet, is already teh effectiv eload capacitance, inlcuing pin capacitance (but not external trace stray capacitance).

goodarz kashian said:

i use two 12pF capacitor connected to each pin as below:

So if the internal capacitance is set to XCAP_0, the resulting CL is 7pF in your case ( (12+2)/2 ).
You shouldn't use both, internal and external caps, at the same time. So if you habve external caps, use the proper ones and don't use the internals (clear the XCAPx bits).

goodarz kashian said:

// Xtal is now stable, reduce drive strength
UCSCTL6 &= ~(XT1DRIVE_3);

This may stop the crystal again, if the lowest drive strength is too low. You should check to be sure it is still operating. (e.g. re-check LFXT1OFFG after some delay)
Or try wihtout this line for testing.

If ACLK is running form REFO, then the tolerance and drift marginds depend on REFO and are shown in the datasheet. If it (finally) runs from the crystal, drift depedns on the crystal.