power fail query

hhh ggg said:

 In case of MSp430F5325, the NMI is shared with /RST on the same pin. Therefore, if we configure the pin to NMI, we will be able to achieve the above objective of saving energy count but will the controller get  reset  from an external reset signal coming from Supervisiory circuit (SP 706)

How could the MSP separate a LOW signal ue to NMI from a low signal that means RST?

If you switch the pin to NMI usage, RST is non functional.

Do you really need NMI? If your ISRs are short enoug (ISRs should be fast-in fast-out and should never do any lengthy operation, for no reason), then a normal interrupt might be okay. You can use any of the P1 or P2 port pins (and the timer's CCRx input pins) to trigger an interrupt on falling edge of a signal and keep RST active for a hard reset.

BTW: If you setup a guard value, you may change your program so that the accumulation value will survive a reset. If the guard value in a variable (which is set by main) is already there at start of main, it is a warm start and you may skip initializing the accumulation variable. (of yourse you must prohibit initialization of both by the C startup code by declaring them as intentionally uninitialized, see your compiler manual for how to do it).
Even a hard reset will keep them intact, while of course on a brownout/power-on they have a random value (hence the guard value). Unfortunately, even the 5x family doesn't tell whether it was a power-on (destructive) or a RST (non destructive to RAM content) that caused a reset. So SYSRSTIV wont help you to tell whether you can use the accumulated value or not. However, a small probability check (e.g. if th evalue is >0.1kWh then it must be bogus) can help to increase performance, even if the guard value is apparently correct (but due to a short brownout, a bit in the accumulated data location has flipped)

hhh ggg said:

 Is there any facility in MSP430F5325 to store energy accumulated count in EEPROM automatically when above situation occurs,if yes how??pl clarify.

I dimly remember an MSP that had some bytes of EAROM or EEPROM besides flash. I just remember because I thought that to be a curiosity.
And some of the MSPs with backup power have some bytes of ram that are retained by this backup power supply. However, unless you directly count in EEPROM/backup ram, there is no automatic way to initiate storage in case of a failure. It must be your software that does this.

Hi,Jens.

Thanks for reply, we have only port 2 is free, suppose we go for the port2 pins which has lowest priority but actually we want  highest priority interrupt.,So is there any facility in MSP430F5325 to change the interrupt priority through software??

hhh ggg said:

we have only port 2 is free, suppose we go for the port2 pins which has lowest priority but actually we want  highest priority interrupt

Any pins on Port6 available? You can use comparator B which have quite high IRQ prio.. And BTW having proper voltage divider, perhaps you can use comparator alone, w/o external voltage monitor.

hhh ggg said:

...

          Pl refer below circuit diagram for Supervisory circuit/attachment ...

In that diagram, what is DVCC1? What is the normal voltage range? Is it expected to be >4.40V? If yes, it cannot be connected to the DVCC or AVCC of the MSP chip. If no, the SP706  will generate a /RESET.

Your stated problem seems to indicate that you want the /PFO output to cause a NMI on the MSP, and the /RESET output to cause a /RST on the MSP.. That means you want to /RST MSP when DVCC1 is below 4.4V and you want to NMI MSP when DVCC1 is below 2.875V (while still being hold in /RST). What good does that do?

hhh ggg said:

we want  highest priority interrupt

I guess this is a misinterpretation of interrupt priorities.
The priority is only of importance if two interrupts compete for execution at the very same time (e.g. both are pending when you set GIE and enable interrupts globally). Then the one with the higher priority will be handled first.
If an ISR is already executing, no other interrupt can interrupt it (even if of higher priority) because during ISR execution, interrupts are disabled. And if you manually enable interrupts inside an ISR (so-called interrupt nesting, which I strongly discourage to use unless you're an expert and really know what you do), then any interrupt will interrupt your ISR, even if of lower priority (including the same interrupt you're currently servicing).

An exception is the NMI, which can interrupt any normal ISR at any time. But this is a different story. Also for real experts.

For many MSP430 (including MSP430F532x) the highest interrupt priority is System NMI, which can be triggered by the SVS/SVM module to monitor power supply..

The OP headed in the wrong direction. See my earlier response.