Harvard vs von neumann, which one's better

Aamir Ali said:

1. So which one's betteror its trade off between two

Which one is better - apple or orange?

When you need fast and determined data memory throughput like for DSP applications, then you choose one. When you need flexibility like execution from RAM, lot of constants in code memory and so on - then choose another. msp430 have right architecture for sure ;)

Why you are asking "1+1" question instead of looking for information? - Here.

Aamir Ali said:

its trade off between two

Yes, of course it is a trade-off!

If one were "better" than the other in all respects, then why would anyone use the other?!

This is a general computer architecture question - it has nothing specifically to do with TI or MSP430 or even microcontollers.

There is plenty of information widely available discussing the merits and demerits of each approach; eg,

http://en.wikipedia.org/wiki/Harvard_architecture

http://en.wikipedia.org/wiki/Von_Neumann_architecture

The main advantage of Harvard architecture is also its greates drawback.

Yes, with 16 bit instructions you can access 192kB memory: 64k of ram and mapped peripherals and 128k of flash (16 bit instruction width). That's great. The ATMega128 uses this.
No need to go for >16 bit address bus when 64k of total memory aren't enough.
But on the downside, you cannot use flash (code memory) stored data easily.
For example printf: to use printf with a format string that is located in code memory, you need a separate version of printf. Because the function cannot determine whether a passed 16 bit pointer points to data memory or code memory. But it needs two completely different instructions to access the two. And passing a constant as additional parameter to printf simply isn't supported at all.
And of course you cannot dynamically load code into ram for execution (I don't know any microcontroller where the code memory contains ram)

The other things mentioned aren't correct.

Yes, in Harvard architecture you can do pipelining easier. Whiel you read the next isntruction, you can read the data for the previous one. This may save you a clock cycle. But this kind of pipelimning also means that you don't make any advantage from having data already in a register. The 'read from ram' stage is a fixed part of the pipeline then, even if it does nothing.
Also, not all Harvard-Architecture-Processors use pipelining at all. This is not a must. Just an option. So the only real difference is the separation of code and data memory.

Btw: the MSP does instruciton prefetching too, if the target of the current isntruciton is not memory but a register (or none). This further reduces the 'execution speed' advantage of the Harvard.

Most of the time, I found the MSP being the faster one compared to the ATMega. Same code, same clock speed. (We use the ATMEga128 for our access point and the MSP for the metering devices, and both share the same codebase for the communication part)