Disabling instruction cache in FRAM controller for Rad-Tolerant application

I think doing that is very risky. A lot more risky as compared to a few SRAM cells that are written and read withing a few microseconds.

Thanks for your reply.  Can you elborate on what is the risk of turning off the instruction cache besides the code runs slower?

I have not seen any documented way to disable the cache. There may exit tricks or undocumented ways to do so and I consider anything done that way risky.

Do you know how to do it? Where is it documented?

I have looked everywhere and couldn't find anything regarding controlling the cache. From the users guide, the cache works when the MPU is running at speed higher then 8MHz when the FRAM access has wait states.  What I am thinking is if I run the MPU at a lower speed, like 1MHz, there seems to be no reason for caching and I wonder if the cache will  be bypassed?

Have you read http://cdn.intechopen.com/pdfs/16181/InTech-Use_of_fram_memories_in_spacecrafts.pdf ?

In the FeRAM weakness section it makes the point that unless the whole device has been designed as Rad Hard an upset in CMOS control logic could corrupt several FRAM cells. i.e. even if the cache could be disabled, what prevents an upset from causing an unwanted write to FRAM?

Thanks for your pointer.