Msp430g2553 master itg3200 gyro slave i2c problem

My understanding that on transmit part, UCB0TXBUF is a 8 bit register so it is trying to transmit 8 bits into the slave. But i need to send 7 bit following by a repeated start. Does this mean that i cannot use the specified state machine on g2553?

Well, I2C is 8 bit. Period.

If the slave requires 7 bit only, then it isn't using I2C but something different.

But perhaps it only means that it takes a 7-bit value  (0-127) even though the data byte transmitted is  8 bit. (MSB must be 0).

However...

    int RXByteCtr, RPT_Flag = 0; // enables repeated start when 1

It is 0, so no repeated start.
You make a send, then send a stop, then init for RX (resetting the USCI) and then receive. No repeated start. What you observed on the scope is exactly what you would expect when going through the code step by step (not in the debugger, but simply on the printed source)

Hello and thanks for your answer in short time. 

If you have read the datasheet that i provided for Itg3200, in the single byte reading sequence, it has been shown that after the first 7bit slave address - R/W - ACK sequence, which is general in all I2c, 7-bit register address followed with an ACK and a repeated start. Here is the figure : 

Note that all I2c address are 7-bit long but normally followed by a R/W. 

Another issue is that Repeated start flag in my code clearly indicates a repeated start. Even though it is 0 in the initiation, RPT_Flag = 1; after the SetupTX() meaning before the Start Condition.

Putting all this aside, I've been checking the Adruino codes coming with this device. After i checked a fully operating bus in oscillator, i realised that they do not use a repeated start like in the sequence but a Stop-Start condition. So actually, the sequence that device use actually look like this:

So it's quite similar to the code example msp430g2xx3_uscib0_i2c_12.c. I changed a little bit and the code came out like this:

#include <msp430.h>

unsigned char *PRxData; // Pointer to RX data
unsigned char RX = 0;
unsigned char MSData = 0x1C;

void Setup_TX(void);
void Setup_RX(void);
void Transmit(void);
void Receive(void);

int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1SEL |= BIT6 + BIT7; // Assign I2C pins to USCI_B0
P1SEL2|= BIT6 + BIT7; // Assign I2C pins to USCI_B0
while(1){

//Transmit process
Setup_TX();
Transmit();
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent

//Receive process
Setup_RX();
Receive();
UCB0CTL1 |= UCTXSTP;
}
}

//-------------------------------------------------------------------------------
// The USCI_B0 data ISR is used to move received data from the I2C slave
// to the MSP430 memory. It is structured such that it can be used to receive
// any 2+ number of bytes by pre-loading RXByteCtr with the byte count.
//-------------------------------------------------------------------------------
#pragma vector = USCIAB0TX_VECTOR
__interrupt void USCIAB0TX_ISR(void)
{
if(RX == 1){ // Master Recieve?
UCB0CTL1 |= UCTXSTP;
*PRxData = UCB0RXBUF; // Move final RX data to PRxData
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}

else{ // Master Transmit
UCB0CTL1 |= UCTXSTP; // I2C stop condition
IFG2 &= ~UCB0TXIFG; // Clear USCI_B0 TX int flag
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}
}

void Setup_TX(void){
_DINT();
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x69; // Slave Address is 069h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
RX = 0; //Transmit mode
IE2 &= ~UCB0RXIE; //Disable RX Interrupt
IE2 |= UCB0TXIE; // Enable TX interrupt

}
void Setup_RX(void){
_DINT();
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x69; // Slave Address is 069h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
RX = 1; //Receive mode
IE2 &= ~UCB0TXIE; //Disable TX Interrupt
IE2 |= UCB0RXIE; // Enable RX interrupt
}
void Transmit(void){
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
UCB0TXBUF = MSData; // MSData into TX Buffer
UCB0CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition
__bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
}
void Receive(void){
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
// UCB0CTL1 &= ~UCTR //Clearing UCTR
UCB0CTL1 |= UCTXSTT; // I2C start condition
__bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
}

I tried this code today in the lab and saw that it locks down the busses to LOW. Since i have no luxury to have a oscilloscope in my house, tomorrow i will post out the lock results as a capture from the oscilloscope. Please keep in touch because i really need to fix this. I could not really come up with a good and clear example similar to what i'm trying to obtain here. TI examples have somehow a bit high-level comments in my opinion :) Maybe this can help more people in my position.

Barışcan Kayaoğlu said:

Note that all I2c address are 7-bit long but normally followed by a R/W. 

That's how I2C is specified.

Yes, the register address is a 7 bit vlaue. But that only means that the MSB of the RA byte has to be blank.

In your case, you don't want to send a stop condition when the write is done. But you also don't want to reconfigure the USCI (especially set UCSWRST) between the two transmission.

Problem is that the demo code ensbales RXIE and TXIE isniode the SETUP funcitons - but also reset the USCI in these.

What you'd need is to setup the USCI, enable RXIE and TXIE if you  want interrupts (in I2C mode, only one of them can ever occur, depending on UCTR, so it is safe to have both enabled) and set the repeates start flag if using these ISRs. So the TX ISR won't set UCTXSTP when al data is sent, before ending LPM.
Then after waking from transmit, you simply call receive. No call of Setup_RX before!

When the datasheet point out the bit counts in the sequence that i provided, i realised that all periods are 9 bit periods. But since the register address is 7 bit and no R/W followed by, i thought that its a 8-bit period. So MSB can be 0 to make it 8-bit, thanks for making me realise that.

Let me get this straight, So if i make an initialization with both RXIE and TXIE flags, it will work? Because i always thought that setting the TXIE flag and UCTR will give the rights to the master so that master holds the bus, preventing slaves to write anything. And for a repeated start, do i just need to set the UCTXSTT and that starts the state machine even without a stop condition?

Hello again.

I'm at the school lab right now trying to accomplish what you said earlier. Here is the code that I am using:

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* for an API functional library-approach to peripheral configuration.
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//******************************************************************************
// MSP430G2xx3 Demo - USCI_B0 I2C Master TX/RX multiple bytes from MSP430 Slave
// with a repeated start in between TX and RX operations.
//
// Description: This demo connects two MSP430's via the I2C bus. The master
// transmits to the slave, then a repeated start is generated followed by a
// receive operation. This is the master code. This code demonstrates how to
// implement an I2C repeated start with the USCI module using the USCI_B0 TX
// interrupt.
// ACLK = n/a, MCLK = SMCLK = BRCLK = default DCO = ~1.2MHz
//
// ***to be used with msp430x22x4_uscib0_i2c_13.c***
//
// /|\ /|\
// MSP430F24x 10k 10k MSP430G2xx3
// slave | | master
// ----------------- | | -----------------
// -|XIN P3.1/UCB0SDA|<-|---+->|P3.1/UCB0SDA XIN|-
// | | | | |
// -|XOUT | | | XOUT|-
// | P3.2/UCB0SCL|<-+----->|P3.2/UCB0SCL |
// | | | |
//
// D. Dang
// Texas Instruments Inc.
// February 2011
// Built with CCS Version 4.2.0 and IAR Embedded Workbench Version: 5.10
//******************************************************************************
#include <msp430.h>

int RXByteCtr;
volatile unsigned char RxBuffer[128]; // Allocate 128 byte of RAM
unsigned char *PTxData; // Pointer to TX data
unsigned char *PRxData; // Pointer to RX data
unsigned char TXByteCtr, Rx = 0;
unsigned char WHO_AM_I = 0x00;

void init_I2C(void);
void Transmit(void);
void Receive(void);

int main(void)
{
WDTCTL = WDTPW + WDTHOLD; // Stop WDT
P1SEL |= BIT6 + BIT7; // Assign I2C pins to USCI_B0
P1SEL2|= BIT6 + BIT7; // Assign I2C pins to USCI_B0
init_I2C();
while(1){
//Transmit process
Rx = 0;
UCB0TXBUF = WHO_AM_I;
Transmit();
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent

//Receive process
Rx = 1;
UCB0CTL1 &= ~UCTR ; // Clear UCTR
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
}
}

//-------------------------------------------------------------------------------
// The USCI_B0 data ISR is used to move received data from the I2C slave
// to the MSP430 memory. It is structured such that it can be used to receive
//-------------------------------------------------------------------------------
#pragma vector = USCIAB0TX_VECTOR
__interrupt void USCIAB0TX_ISR(void)
{
if(Rx == 1){ // Master Recieve?
UCB0CTL1 |= UCTXSTP;
*PRxData = UCB0RXBUF; // Move final RX data to PRxData
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}

else{ // Master Transmit
//UCB0CTL1 |= UCTXSTP; // I2C stop condition
//IFG2 &= ~UCB0TXIFG; // Clear USCI_B0 TX int flag
__bic_SR_register_on_exit(CPUOFF); // Exit LPM0
}

}

void init_I2C(void) {
_DINT();
IE2 |= UCB0RXIE; //Enable RX interrupt
IE2 |= UCB0TXIE; // Enable TX interrupt
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
UCB0CTL1 |= UCSWRST; // Enable SW reset
UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
UCB0BR1 = 0;
UCB0I2CSA = 0x69; // Slave Address is 069h
UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
}

void Transmit(void){
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
UCB0CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition
__bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
}
void Receive(void){
while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
UCB0CTL1 |= UCTXSTT; // I2C start condition
__bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
}

 I have tried with a repeated start first, then with a stop condition between them, but the outcome rest the same. Both SCL and SDA busses locked down to 0V somehow and SDA does not ever change if i do not remove the bus and put it on again.

Here is another cleaner version that i combined a single read and write examples of TI, but still SDA and SCL locks down somehow.

#include <msp430.h>

int TXByteCtr = 1;
unsigned char PRxData; // Pointer to RX data
int Rx = 0;
unsigned char WHO_AM_I = 0x00;

void init_I2C(void);
void Transmit(void);
void Receive(void);

int main(void)
{
    WDTCTL = WDTPW + WDTHOLD; // Stop WDT
    P1SEL |= BIT6 + BIT7; // Assign I2C pins to USCI_B0
    P1SEL2|= BIT6 + BIT7; // Assign I2C pins to USCI_B0
    init_I2C();
    while(1){
        //Transmit process
        Rx = 0;
        UCB0TXBUF = WHO_AM_I;
        Transmit();
        while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent

        //Receive process
        Rx = 1;
        Receive();
        while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
        }
}

//-------------------------------------------------------------------------------
// The USCI_B0 data ISR is used to move received data from the I2C slave
// to the MSP430 memory. It is structured such that it can be used to receive
//-------------------------------------------------------------------------------
#pragma vector = USCIAB0TX_VECTOR
__interrupt void USCIAB0TX_ISR(void)
{
    if(Rx == 1){     // Master Recieve?
         PRxData = UCB0RXBUF; // Get RX data
         __bic_SR_register_on_exit(CPUOFF); // Exit LPM0
    }

    else{     // Master Transmit
        if (TXByteCtr) // Check TX byte counter
        {
            UCB0TXBUF = WHO_AM_I; // Load TX buffer
            TXByteCtr--; // Decrement TX byte counter
        }
        else
        {
            UCB0CTL1 |= UCTXSTP; // I2C stop condition
            IFG2 &= ~UCB0TXIFG; // Clear USCI_B0 TX int flag
            __bic_SR_register_on_exit(CPUOFF); // Exit LPM0
        }
}

}

void init_I2C(void) {
    _DINT();
    IE2 |= UCB0RXIE; //Enable RX interrupt
    IE2 |= UCB0TXIE; // Enable TX interrupt
    while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
    UCB0CTL1 |= UCSWRST; // Enable SW reset
    UCB0CTL0 = UCMST + UCMODE_3 + UCSYNC; // I2C Master, synchronous mode
    UCB0CTL1 = UCSSEL_2 + UCSWRST; // Use SMCLK, keep SW reset
    UCB0BR0 = 12; // fSCL = SMCLK/12 = ~100kHz
    UCB0BR1 = 0;
    UCB0I2CSA = 0x69; // Slave Address is 069h
    UCB0CTL1 &= ~UCSWRST; // Clear SW reset, resume operation
}

void Transmit(void){
    while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
    UCB0CTL1 |= UCTR + UCTXSTT; // I2C TX, start condition
    __bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
}
void Receive(void){
    UCB0CTL1 &= ~UCTR ; // Clear UCTR
    while (UCB0CTL1 & UCTXSTP); // Ensure stop condition got sent
    UCB0CTL1 |= UCTXSTT; // I2C start condition
    while (UCB0CTL1 & UCTXSTT); // Start condition sent?
    UCB0CTL1 |= UCTXSTP; // I2C stop condition
    __bis_SR_register(CPUOFF + GIE); // Enter LPM0 w/ interrupts
}