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DCO high frequency output.

Paul Young
Intellectual 310 points

Other Parts Discussed in Thread: MSP430F6638

I'm using a MSP430f6638 which as I understand it the fastest you can clock MCLK is at 20MHz.

When would you use the DCO to generate a frequency of between 60MHz to 135MHz as described in the datasheet for the 6638?

  • TI__Mastermind 26380 points

    Since a frequency > 20MHz cannot be used anywhere in the system, the answer is 'no'. You would be violating the Fsystem specification and overclocking the device.

    Regards,

    Priya

  • in reply to Priya Thanigai
    Intellectual 310 points

    I thought that might be the case. So what's the thinking behind the design of the DCO to allow one to generate such high frequencies?

  • in reply to Paul Young
    Expert 2870 points

    Surprisingly XT2 is also capable of 32MHz.

  • Guru 12160 points

    Hi Paul,

    Yes the DCO can generate higher frequencies than you can use for MCLK, SMCLK, ACLK, etc.  Similarly, the XT2 crystal oscillator on many 5xx and 6xx devices allows up to 32MHz even though you can't route that full speed to MCLK, SMCLK, etc.

    Why is the overspeed DCO useful?  Some people like to run a fast DCO and allow DCOCLKDIV to drive MCLK/SMCLK/etc.  DCOCLKDIV is slightly insulated from the negative effects of clock modulation applied to DCOCLK in that case.

    However, in practice, anything more than divide-by-two doesn't really buy you much.  For example, DCOCLK = 60MHz with DCOCLKDIV = 15MHz isn't really much better than DCOCLK=30MHz and DCOCLKDIV=15MHz.  And in general, folks seem to prefer the lower-power approach (divide-by-two).

    Jeff

  • Guru 227245 points

    Paul Young said:
    When would you use the DCO to generate a frequency of between 60MHz to 135MHz as described in the datasheet for the 6638?

    While ht emaximum MCLK speed (adn system clock speed) is indeed 20 or 25MHZ (depending on MSP), the maximum DCO speed is indeeed much higher.
    You can't use this directly fo rMCLK. But you can run the DCO on, say 40MHz and use DCOCLKDIV for MCLK.
    This will reduce clock jitter when using DCO modulation to get your desired frequency.

    If you set the DCO for 128MHz (with modulation) so that DCODIV results in 4MHz, those 4MHz will be free from any modulation jitter. Which could be required for furthe rusage. Or you have DCODIV=16MHz and use SMCLK=DOCDIV/4. Then MCLK will be 16MHz with some small jitter (but unimportant) but SMCLK will be jitter-free.

    It also gives you more possible combinations of DCOCLK, DCOCLKDIV and reference when trying to get an exact output frequency using the FLL.

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